{"id":"https://openalex.org/W1587718955","doi":"https://doi.org/10.1109/fpt.2002.1188733","title":"Alternatives in FPGA-based SAD implementations","display_name":"Alternatives in FPGA-based SAD implementations","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1587718955","doi":"https://doi.org/10.1109/fpt.2002.1188733","mag":"1587718955"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036463224","display_name":"Stephan Wong","orcid":"https://orcid.org/0000-0003-3521-2612"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Wong","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technnology, Netherlands","Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technnology, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022598584","display_name":"B. Stougie","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"B. Stougie","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technnology, Netherlands","Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technnology, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057424352","display_name":"Sorin Cot\u00f6fan\u0103","orcid":"https://orcid.org/0000-0001-7132-2291"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Cotofana","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technnology, Netherlands","Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technnology, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Comput. Eng. Lab, Delft Univ. of Technol., Netherlands#TAB#","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":1.2716,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.77365549,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"449","last_page":"452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11439","display_name":"Video Analysis and Summarization","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8270031213760376},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7905031442642212},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7846089601516724},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5815135836601257},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5643643736839294},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5371302962303162},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4304943084716797},{"id":"https://openalex.org/keywords/software-implementation","display_name":"Software implementation","score":0.41980844736099243},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.404110312461853},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38578587770462036},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11427414417266846},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07338085770606995}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8270031213760376},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7905031442642212},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7846089601516724},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5815135836601257},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5643643736839294},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5371302962303162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4304943084716797},{"id":"https://openalex.org/C2983609787","wikidata":"https://www.wikidata.org/wiki/Q10534782","display_name":"Software implementation","level":3,"score":0.41980844736099243},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.404110312461853},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38578587770462036},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11427414417266846},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07338085770606995},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2002.1188733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.1.5918","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.5918","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ce.et.tudelft.nl/publicationfiles/734_14_fpt2002.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Quality Education","id":"https://metadata.un.org/sdg/4","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W198709078","https://openalex.org/W204342094","https://openalex.org/W1482960371","https://openalex.org/W1489518132","https://openalex.org/W1992393251","https://openalex.org/W2114761930","https://openalex.org/W2143740079","https://openalex.org/W2149521703","https://openalex.org/W2155430240","https://openalex.org/W2168569016","https://openalex.org/W3146150975","https://openalex.org/W6608173102","https://openalex.org/W6682806288"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W2390807153","https://openalex.org/W2538906952"],"abstract_inverted_index":{"In":[0,37],"multimedia":[1],"processing,":[2],"it":[3],"is":[4,11,26],"well-known":[5],"that":[6,60,121],"the":[7,12,30,46,51,67,95,110,122,144,149],"sum-of-absolute-differences":[8],"(SAD)":[9],"operation":[10,15,48],"most":[13,52],"time-consuming":[14],"when":[16],"implemented":[17,80],"in":[18,55,70,140],"software":[19,100,112],"running":[20],"on":[21],"programmable":[22],"processor":[23],"cores.":[24],"This":[25,130],"mainly":[27],"due":[28],"to":[29],"sequential":[31],"characteristic":[32],"of":[33,45,72,148],"such":[34,82],"an":[35,61],"implementation.":[36],"this":[38],"paper,":[39],"we":[40],"investigate":[41],"several":[42],"hardware":[43],"implementations":[44],"SAD":[47],"and":[49,74,77,105],"map":[50],"promising":[53],"one":[54],"FPGA.":[56],"Our":[57],"investigation":[58],"shows":[59],"adder":[62],"tree":[63],"based":[64],"approach":[65],"yields":[66],"best":[68],"results":[69,119],"terms":[71],"speed":[73],"area":[75],"requirements":[76],"has":[78],"been":[79],"as":[81],"by":[83,93,108],"writing":[84],"high-level":[85],"VHDL":[86],"code.":[87],"The":[88],"design":[89,123],"was":[90],"functionally":[91],"verified":[92],"utilizing":[94,109],"MAX+plus":[96],"II":[97],"10.1":[98],"Baseline":[99],"package":[101,113],"from":[102,114],"Altera":[103],"Corp.":[104],"then":[106],"synthesized":[107],"LeonardoSpectrum":[111],"Exemplar":[115],"Logic":[116],"Inc.":[117],"Preliminary":[118],"show":[120],"can":[124],"be":[125],"clocked":[126],"at":[127],"380":[128],"MHz.":[129],"result":[131],"translates":[132],"into":[133],"a":[134],"faster":[135],"than":[136],"real-time":[137],"full":[138],"search":[139],"motion":[141],"estimation":[142],"for":[143],"main":[145],"profile/main":[146],"level":[147],"MPEG-2":[150],"standard.":[151]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}