{"id":"https://openalex.org/W1593620144","doi":"https://doi.org/10.1109/fpt.2002.1188728","title":"A method of implementing bit-serial LDI ladder filters in FPGAs using JBits","display_name":"A method of implementing bit-serial LDI ladder filters in FPGAs using JBits","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1593620144","doi":"https://doi.org/10.1109/fpt.2002.1188728","mag":"1593620144"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080279481","display_name":"A. Carreira","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Carreira","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046902116","display_name":"T.W. Fox","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"T.W. Fox","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005447330","display_name":"L.E. Turner","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"L.E. Turner","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Calgary Univ., Alta., Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I168635309"],"apc_list":null,"apc_paid":null,"fwci":0.3179,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.45284489,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"433","last_page":"436"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8122363090515137},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7379838824272156},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5866257548332214},{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.5171891450881958},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.5115429162979126},{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.48358768224716187},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.47473201155662537},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.4669561982154846},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.44980210065841675},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3537285625934601},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24787363409996033},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.17060798406600952},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.09840652346611023},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09243372082710266}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8122363090515137},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7379838824272156},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5866257548332214},{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.5171891450881958},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.5115429162979126},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.48358768224716187},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.47473201155662537},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.4669561982154846},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.44980210065841675},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3537285625934601},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24787363409996033},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.17060798406600952},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.09840652346611023},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09243372082710266},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2002.1188728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W76355380","https://openalex.org/W1507071772","https://openalex.org/W1537817240","https://openalex.org/W1766888123","https://openalex.org/W1840087777","https://openalex.org/W1985864836","https://openalex.org/W2083019134","https://openalex.org/W2141833038","https://openalex.org/W2172151141","https://openalex.org/W2478884216"],"related_works":["https://openalex.org/W2080235730","https://openalex.org/W2534868112","https://openalex.org/W2694160303","https://openalex.org/W4297665406","https://openalex.org/W3028347934","https://openalex.org/W2387631519","https://openalex.org/W2749962643","https://openalex.org/W2784192210","https://openalex.org/W2185692674","https://openalex.org/W2973221965"],"abstract_inverted_index":{"A":[0,78],"simulated":[1],"annealing":[2],"design":[3,79],"method":[4,30,55,84],"for":[5,65],"low":[6],"hardware":[7,41,71,92],"cost":[8,72,93],"bit-serial":[9,47,76],"Lossless":[10],"Discrete":[11],"Integrator":[12],"(LDI)":[13],"recursive":[14],"digital":[15],"filter":[16,40],"implementations":[17],"using":[18,56,81],"Field":[19],"Programmable":[20],"Gate":[21],"Arrays":[22],"(FPGAs)":[23],"with":[24],"JBits/spl":[25,57],"trade/":[26,58],"is":[27,49,85,95],"presented.":[28],"This":[29],"jointly":[31],"minimizes":[32],"the":[33,39,70,82],"magnitude":[34],"frequency":[35],"response":[36],"error":[37],"and":[38],"cost.":[42],"The":[43],"next-neighbor":[44],"connectivity":[45],"of":[46,75],"systems":[48],"exploited":[50],"to":[51,59,69],"create":[52],"a":[53,89],"placement":[54,63],"avoid":[60],"time-consuming":[61],"general-purpose":[62],"tools":[64],"FPGAs":[66],"in":[67,87],"addition":[68],"reduction":[73,94],"benefits":[74],"architectures.":[77],"example":[80],"proposed":[83],"presented":[86],"which":[88],"30.2":[90],"percent":[91],"obtained.":[96]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
