{"id":"https://openalex.org/W1579151910","doi":"https://doi.org/10.1109/fpt.2002.1188716","title":"Field modifiable architecture with FPGAs and its design methodology","display_name":"Field modifiable architecture with FPGAs and its design methodology","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1579151910","doi":"https://doi.org/10.1109/fpt.2002.1188716","mag":"1579151910"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188716","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188716","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050673369","display_name":"Setsuko Komatsu","orcid":"https://orcid.org/0000-0002-4514-357X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"S. Komatsu","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, , Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, , Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004839395","display_name":"Yohei Kojima","orcid":"https://orcid.org/0000-0003-4790-6312"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Kojima","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, , Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, , Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111873088","display_name":"Hirobumi Saito","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Saito","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, , Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, , Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037874806","display_name":"K. Seto","orcid":"https://orcid.org/0000-0001-9043-7019"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Seto","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, , Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, , Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Fujita","raw_affiliation_strings":["University of Tokyo, Japan","University of Tokyo, , Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"University of Tokyo, , Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050673369"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05942523,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"382","last_page":"385"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8150464296340942},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6997776031494141},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6582521200180054},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6396843791007996},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6290912628173828},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.60187166929245},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.5398406982421875},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.5289302468299866},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5287308692932129},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4959629476070404},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4927826225757599},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.4641844630241394},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4289705157279968},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17888739705085754}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8150464296340942},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6997776031494141},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6582521200180054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6396843791007996},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6290912628173828},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.60187166929245},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.5398406982421875},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.5289302468299866},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5287308692932129},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4959629476070404},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4927826225757599},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.4641844630241394},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4289705157279968},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17888739705085754},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2002.1188716","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188716","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2090385753","https://openalex.org/W2142570900","https://openalex.org/W6680889965"],"related_works":["https://openalex.org/W3200538824","https://openalex.org/W1990473394","https://openalex.org/W1977643363","https://openalex.org/W2902230348","https://openalex.org/W2070693700","https://openalex.org/W1561071093","https://openalex.org/W2097839191","https://openalex.org/W1501340521","https://openalex.org/W2069543777","https://openalex.org/W2028269328"],"abstract_inverted_index":{"In":[0,74],"the":[1,8,20,35],"age":[2],"of":[3,10,34,70,105],"highly":[4],"integrated":[5],"system":[6,31],"LSIs,":[7],"problem":[9],"design":[11,66,72,90],"methodologies":[12],"with":[13],"short":[14],"time-to-market":[15],"and":[16,51,88],"higher":[17,52],"re-programmability":[18],"after":[19],"chip":[21],"fabrications":[22],"has":[23],"acquired":[24],"great":[25],"importance.":[26],"Although":[27],"a":[28,59,79],"pure":[29],"FPGA":[30],"is":[32],"one":[33],"solutions,":[36],"it":[37],"cannot":[38],"give":[39,64],"sufficient":[40],"performance":[41,50,101],"in":[42,68,103],"many":[43],"real-time":[44],"applications":[45],"due":[46],"to":[47,56],"its":[48,89],"lower":[49],"power":[53],"dissipation":[54],"compared":[55],"ASICs.":[57],"Instead,":[58],"hardware/software":[60],"co-design":[61],"approach":[62],"can":[63,98],"best":[65],"solutions":[67],"terms":[69,104],"such":[71],"criteria.":[73],"this":[75],"paper,":[76],"we":[77],"introduce":[78],"new":[80],"VLSI":[81],"architecture":[82,97],"called":[83],"Field":[84],"Modifiable":[85],"Architecture":[86],"(FMA)":[87],"methodology.":[91],"Experimental":[92],"results":[93],"confirm":[94],"that":[95],"our":[96],"achieve":[99],"significant":[100],"improvement":[102],"execution":[106],"cycles.":[107]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
