{"id":"https://openalex.org/W1550490085","doi":"https://doi.org/10.1109/fpt.2002.1188710","title":"Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs","display_name":"Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1550490085","doi":"https://doi.org/10.1109/fpt.2002.1188710","mag":"1550490085"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188710","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188710","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041797098","display_name":"A. Benkrid","orcid":"https://orcid.org/0000-0003-2524-5875"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Benkrid","raw_affiliation_strings":["School of Computer Science, Queen''s University Belfast, Belfast, UK","Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, Queen''s University Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111836086","display_name":"K. Benkrid","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"K. Benkrid","raw_affiliation_strings":["School of Computer Science, Queen''s University Belfast, Belfast, UK","Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, Queen''s University Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000739686","display_name":"Danny Crookes","orcid":"https://orcid.org/0000-0002-3533-6095"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. Crookes","raw_affiliation_strings":["School of Computer Science, Queen''s University Belfast, Belfast, UK","Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, Queen''s University Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"Sch. of Comput. Sci., Queen's Univ., Belfast, UK#TAB#","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I126231945"],"apc_list":null,"apc_paid":null,"fwci":1.5895,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81590023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"356","last_page":"359"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7462468147277832},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.7393848896026611},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7146875858306885},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.632466197013855},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5538840293884277},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4936145544052124},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.46542972326278687},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4485517740249634},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4309743642807007},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38981032371520996},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38611990213394165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3677539825439453},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32669463753700256},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1879172921180725}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7462468147277832},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.7393848896026611},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7146875858306885},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.632466197013855},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5538840293884277},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4936145544052124},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.46542972326278687},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4485517740249634},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4309743642807007},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38981032371520996},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38611990213394165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3677539825439453},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32669463753700256},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1879172921180725},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2002.1188710","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188710","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1501488688","https://openalex.org/W1504737862","https://openalex.org/W1560308971","https://openalex.org/W1587217691","https://openalex.org/W1607038717","https://openalex.org/W2039517429","https://openalex.org/W2101789093","https://openalex.org/W6635218997"],"related_works":["https://openalex.org/W2352374383","https://openalex.org/W1980880153","https://openalex.org/W4210376836","https://openalex.org/W4210925376","https://openalex.org/W1633995705","https://openalex.org/W2596211269","https://openalex.org/W2360384790","https://openalex.org/W4232397253","https://openalex.org/W4235913033","https://openalex.org/W2039966832"],"abstract_inverted_index":{"Symmetric":[0],"FIR":[1,27],"filters,":[2],"which":[3,46,109],"provide":[4],"linear":[5],"phases,":[6],"are":[7],"frequently":[8],"used":[9],"in":[10,48,152],"digital":[11],"signal":[12,44,51],"processing.":[13],"This":[14],"paper":[15],"presents":[16],"the":[17,40,72,75,79,102,111,132,139,150],"design":[18],"and":[19,66,77],"implementation":[20,86,137],"of":[21,42,74,81,104,134],"a":[22,98,106,135],"novel":[23],"architecture":[24,34,62,129],"for":[25,38],"symmetric":[26],"filters":[28],"on":[29,57,97],"Xilinx":[30,82],"Virtex":[31,83],"FPGAs.":[32,84],"The":[33,85,115],"is":[35,63,117,142,149],"particularly":[36],"useful":[37],"handling":[39],"problem":[41],"processing":[43,52,113],"boundaries,":[45],"occurs":[47],"finite":[49],"length":[50],"(e.g.":[53,155],"image":[54],"processing).":[55],"Based":[56],"bit":[58],"parallel":[59],"arithmetic,":[60],"our":[61,128],"fully":[64],"scalable":[65],"parameterised.":[67],"It":[68],"takes":[69],"into":[70],"account":[71],"details":[73],"symmetry":[76],"exploits":[78],"features":[80],"leads":[87],"to":[88,93,122,144],"considerable":[89],"area":[90],"savings":[91],"compared":[92],"conventional":[94,136],"implementations":[95],"(based":[96],"hard":[99],"router),":[100],"at":[101],"expense":[103],"using":[105],"clock":[107],"doubler,":[108],"reduces":[110],"overall":[112],"speed.":[114],"latter":[116],"however":[118],"still":[119],"high":[120],"enough":[121],"achieve":[123],"real":[124],"time":[125],"performance.":[126],"Moreover,":[127],"can":[130],"match":[131],"speed":[133],"if":[138],"filter":[140],"output":[141],"going":[143],"be":[145],"decimated,":[146],"as":[147],"it":[148],"case":[151],"multirate":[153],"applications":[154],"wavelets).":[156]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
