{"id":"https://openalex.org/W1598805563","doi":"https://doi.org/10.1109/fpt.2002.1188705","title":"A novel three phase parallel genetic approach to routing for field programmable gate arrays","display_name":"A novel three phase parallel genetic approach to routing for field programmable gate arrays","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1598805563","doi":"https://doi.org/10.1109/fpt.2002.1188705","mag":"1598805563"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188705","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188705","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"A. Muthukaruppan","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]},{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Muthukaruppan","raw_affiliation_strings":["Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I24676775"]},{"raw_affiliation_string":"Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":null,"display_name":"S. Suresh","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]},{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Suresh","raw_affiliation_strings":["Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I24676775"]},{"raw_affiliation_string":"Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010004459","display_name":"V. Kamakoti","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]},{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. Kamakoti","raw_affiliation_strings":["Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Circuits and VLSI Laboratory, Department of Computer Science and Engineering, Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I24676775"]},{"raw_affiliation_string":"Dept. of Computer Science & Engg., Indian Institute of Technology, Chennai, India","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8615,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68970651,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"5","issue":null,"first_page":"336","last_page":"339"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.8999496698379517},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7929379940032959},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7706547975540161},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.703294575214386},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5934705138206482},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5488444566726685},{"id":"https://openalex.org/keywords/population","display_name":"Population","score":0.5465644598007202},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.44980326294898987},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20409360527992249},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18673521280288696},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.147197425365448}],"concepts":[{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.8999496698379517},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7929379940032959},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7706547975540161},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.703294575214386},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5934705138206482},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5488444566726685},{"id":"https://openalex.org/C2908647359","wikidata":"https://www.wikidata.org/wiki/Q2625603","display_name":"Population","level":2,"score":0.5465644598007202},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.44980326294898987},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20409360527992249},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18673521280288696},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.147197425365448},{"id":"https://openalex.org/C144024400","wikidata":"https://www.wikidata.org/wiki/Q21201","display_name":"Sociology","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C149923435","wikidata":"https://www.wikidata.org/wiki/Q37732","display_name":"Demography","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2002.1188705","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188705","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1554938446","https://openalex.org/W1916650455","https://openalex.org/W1945450593","https://openalex.org/W1983950263","https://openalex.org/W2107375256","https://openalex.org/W2131385043","https://openalex.org/W2505129054","https://openalex.org/W6640180554","https://openalex.org/W6640555737","https://openalex.org/W6679600846"],"related_works":["https://openalex.org/W2358991869","https://openalex.org/W4285173741","https://openalex.org/W1486050759","https://openalex.org/W2309292492","https://openalex.org/W2735105689","https://openalex.org/W1482833264","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W1598805563","https://openalex.org/W2184011203"],"abstract_inverted_index":{"This":[0],"paper":[1],"establishes":[2],"a":[3,17,73],"handshake":[4],"between":[5],"the":[6,20,29,32,36,42,54,58,79],"fields":[7],"of":[8,31,44,52,60,68],"\"parallel":[9],"genetic":[10,61],"algorithms\"":[11],"and":[12],"reconfigurable":[13],"systems,":[14],"to":[15,27,40,63,72],"provide":[16],"solution":[18],"for":[19,23,46],"routing":[21,45],"problem":[22,43],"FPGAs,":[24],"that":[25,75],"attempts":[26],"enhance":[28],"performance":[30],"circuit":[33],"implemented":[34],"by":[35],"FPGA.":[37],"We":[38],"propose":[39],"solve":[41],"FPGAs":[47],"in":[48],"three":[49],"phases,":[50],"out":[51],"which":[53],"first":[55],"two":[56],"utilize":[57],"concept":[59],"algorithms":[62],"transform":[64],"an":[65],"initial":[66],"population":[67,74],"random":[69],"suggested":[70],"routings":[71],"contains":[76],"solutions":[77],"approximating":[78],"optimal":[80],"one.":[81]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}