{"id":"https://openalex.org/W1555527786","doi":"https://doi.org/10.1109/fpt.2002.1188696","title":"Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards","display_name":"Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1555527786","doi":"https://doi.org/10.1109/fpt.2002.1188696","mag":"1555527786"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2002.1188696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113918590","display_name":"S. C. Jain","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S.C. Jain","raw_affiliation_strings":["EE Department, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EE Department, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101478917","display_name":"Anshul Kumar","orcid":"https://orcid.org/0000-0002-3871-5402"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Kumar","raw_affiliation_strings":["CSE Department, IIT, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSE Department, IIT, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107893868","display_name":"Shashi Kumar","orcid":"https://orcid.org/0000-0002-2442-7143"},"institutions":[{"id":"https://openalex.org/I94616838","display_name":"J\u00f6nk\u00f6ping University","ror":"https://ror.org/03t54am93","country_code":"SE","type":"education","lineage":["https://openalex.org/I94616838"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"S. Kumar","raw_affiliation_strings":["University of J\u00f6nk\u00f6ping, Jonkoping, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of J\u00f6nk\u00f6ping, Jonkoping, Sweden","institution_ids":["https://openalex.org/I94616838"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3543,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59440946,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"298","last_page":"301"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9031494855880737},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7780886292457581},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7060227990150452},{"id":"https://openalex.org/keywords/terminal","display_name":"Terminal (telecommunication)","score":0.5580235719680786},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5519357919692993},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5184385776519775},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4478953778743744},{"id":"https://openalex.org/keywords/circuit-switching","display_name":"Circuit switching","score":0.44665688276290894},{"id":"https://openalex.org/keywords/hop","display_name":"Hop (telecommunications)","score":0.42470648884773254},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4151769280433655},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.32839691638946533},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10548058152198792}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9031494855880737},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7780886292457581},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7060227990150452},{"id":"https://openalex.org/C2779664074","wikidata":"https://www.wikidata.org/wiki/Q3518405","display_name":"Terminal (telecommunication)","level":2,"score":0.5580235719680786},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5519357919692993},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5184385776519775},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4478953778743744},{"id":"https://openalex.org/C74294265","wikidata":"https://www.wikidata.org/wiki/Q506273","display_name":"Circuit switching","level":2,"score":0.44665688276290894},{"id":"https://openalex.org/C25906391","wikidata":"https://www.wikidata.org/wiki/Q1432381","display_name":"Hop (telecommunications)","level":2,"score":0.42470648884773254},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4151769280433655},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.32839691638946533},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10548058152198792}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2002.1188696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2002.1188696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2127269626","https://openalex.org/W2130778378"],"related_works":["https://openalex.org/W2122026593","https://openalex.org/W3211557223","https://openalex.org/W2117210722","https://openalex.org/W2007036916","https://openalex.org/W2589759689","https://openalex.org/W2582203024","https://openalex.org/W4206528302","https://openalex.org/W872563264","https://openalex.org/W1588358165","https://openalex.org/W2026804694"],"abstract_inverted_index":{"In":[0,73,155],"rapid":[1],"prototyping":[2],"system":[3],"application,":[4],"any":[5],"large":[6],"digital":[7],"circuit":[8,85,89,99],"can":[9],"be":[10,102],"implemented":[11,92],"onto":[12],"Multi-FPGA":[13],"Board(MFB).":[14],"Key":[15],"MFB":[16,62],"architectural":[17],"feature":[18],"is":[19,91],"its":[20],"inter-FPGA":[21],"connections":[22,29,45],"consisting":[23,39],"of":[24,40,44,67,119,131],"fixed":[25],"connections(FC)":[26],"i.e.":[27,33],"FPGA-FPGA":[28],"and":[30,106],"programmable":[31],"connections(PC)":[32],"FPGA-programmable":[34],"switch":[35],"like":[36],"FPID-FPGA.":[37],"MFBs":[38],"both":[41],"the":[42,96,117,143,160],"types":[43],"are":[46,79,113],"known":[47],"as":[48,56],"hybrid":[49],"MFBs.":[50],"Since,":[51],"PC":[52],"requires":[53],"two":[54],"wires":[55],"against":[57],"one":[58,82,94],"wire":[59],"in":[60,150],"FC,":[61],"must":[63],"have":[64],"minimum":[65],"number":[66,130],"PCs":[68,105],"to":[69,115,125,137,162],"keep":[70],"fabrication":[71],"easy.":[72],"partitioned":[74],"circuit,":[75],"multi-terminal":[76,164],"nets":[77],"(MTNs)":[78],"distributed":[80],"over":[81,93,104],"or":[83],"more":[84],"parts.":[86],"When":[87],"each":[88],"part":[90],"FPGA,":[95],"MTNs":[97],"between":[98,108],"parts":[100],"will":[101],"routed":[103],"FCs":[107],"corresponding":[109],"FPGAs.":[110],"Multi-hop":[111],"routers":[112],"used":[114],"minimize":[116],"use":[118],"PCs,":[120],"but":[121],"they":[122],"increase":[123],"source":[124],"sink":[126],"delay":[127],"with":[128],"increasing":[129],"hops.":[132],"A":[133],"generic":[134],"multi-hop":[135],"router":[136],"route":[138,163],"two-terminal":[139],"nets,":[140],"which":[141],"obeys":[142],"given":[144],"limit":[145],"on":[146],"hops,":[147],"was":[148],"presented":[149],"our":[151],"previous":[152],"work":[153],"[2002].":[154],"this":[156],"paper,":[157],"we":[158],"extend":[159],"same":[161],"nets.":[165]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
