{"id":"https://openalex.org/W7140845379","doi":"https://doi.org/10.1109/fpl68686.2025.00046","title":"Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems","display_name":"Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems","publication_year":2025,"publication_date":"2025-09-01","ids":{"openalex":"https://openalex.org/W7140845379","doi":"https://doi.org/10.1109/fpl68686.2025.00046"},"language":null,"primary_location":{"id":"doi:10.1109/fpl68686.2025.00046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035433965","display_name":"Riadh Ben Abdelhamid","orcid":"https://orcid.org/0000-0001-8504-4739"},"institutions":[{"id":"https://openalex.org/I223822909","display_name":"Heidelberg University","ror":"https://ror.org/038t36y30","country_code":"DE","type":"education","lineage":["https://openalex.org/I223822909"]},{"id":"https://openalex.org/I4210086570","display_name":"Heidelberg University of Education","ror":"https://ror.org/0044w3h23","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210086570"]},{"id":"https://openalex.org/I4210127657","display_name":"Heidelberg Engineering (Germany)","ror":"https://ror.org/03thsxs59","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210127657"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Riadh Ben Abdelhamid","raw_affiliation_strings":["Heidelberg University,Dept. Computer Engineering,Germany"],"affiliations":[{"raw_affiliation_string":"Heidelberg University,Dept. Computer Engineering,Germany","institution_ids":["https://openalex.org/I4210127657","https://openalex.org/I4210086570","https://openalex.org/I223822909"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045431998","display_name":"Vladislav V\u00e1lek","orcid":null},"institutions":[{"id":"https://openalex.org/I223822909","display_name":"Heidelberg University","ror":"https://ror.org/038t36y30","country_code":"DE","type":"education","lineage":["https://openalex.org/I223822909"]},{"id":"https://openalex.org/I4210086570","display_name":"Heidelberg University of Education","ror":"https://ror.org/0044w3h23","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210086570"]},{"id":"https://openalex.org/I4210127657","display_name":"Heidelberg Engineering (Germany)","ror":"https://ror.org/03thsxs59","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210127657"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Vladislav Valek","raw_affiliation_strings":["Heidelberg University,Dept. Computer Engineering,Germany"],"affiliations":[{"raw_affiliation_string":"Heidelberg University,Dept. Computer Engineering,Germany","institution_ids":["https://openalex.org/I4210127657","https://openalex.org/I4210086570","https://openalex.org/I223822909"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089447290","display_name":"K. Klein","orcid":"https://orcid.org/0000-0002-0047-2994"},"institutions":[{"id":"https://openalex.org/I223822909","display_name":"Heidelberg University","ror":"https://ror.org/038t36y30","country_code":"DE","type":"education","lineage":["https://openalex.org/I223822909"]},{"id":"https://openalex.org/I4210086570","display_name":"Heidelberg University of Education","ror":"https://ror.org/0044w3h23","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210086570"]},{"id":"https://openalex.org/I4210127657","display_name":"Heidelberg Engineering (Germany)","ror":"https://ror.org/03thsxs59","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210127657"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Kevin Klein","raw_affiliation_strings":["Heidelberg University,Dept. Computer Engineering,Germany"],"affiliations":[{"raw_affiliation_string":"Heidelberg University,Dept. Computer Engineering,Germany","institution_ids":["https://openalex.org/I4210127657","https://openalex.org/I4210086570","https://openalex.org/I223822909"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064000482","display_name":"Dirk Koch","orcid":"https://orcid.org/0000-0002-2568-4432"},"institutions":[{"id":"https://openalex.org/I223822909","display_name":"Heidelberg University","ror":"https://ror.org/038t36y30","country_code":"DE","type":"education","lineage":["https://openalex.org/I223822909"]},{"id":"https://openalex.org/I4210086570","display_name":"Heidelberg University of Education","ror":"https://ror.org/0044w3h23","country_code":"DE","type":"education","lineage":["https://openalex.org/I4210086570"]},{"id":"https://openalex.org/I4210127657","display_name":"Heidelberg Engineering (Germany)","ror":"https://ror.org/03thsxs59","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210127657"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dirk Koch","raw_affiliation_strings":["Heidelberg University,Dept. Computer Engineering,Germany"],"affiliations":[{"raw_affiliation_string":"Heidelberg University,Dept. Computer Engineering,Germany","institution_ids":["https://openalex.org/I4210127657","https://openalex.org/I4210086570","https://openalex.org/I223822909"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5035433965"],"corresponding_institution_ids":["https://openalex.org/I223822909","https://openalex.org/I4210086570","https://openalex.org/I4210127657"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6742341,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"282","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.323199987411499,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.323199987411499,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.23690000176429749,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.16750000417232513,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5712000131607056},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5600000023841858},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5227000117301941},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.43790000677108765},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.3837999999523163},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.3695000112056732},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.3578999936580658}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6353999972343445},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5712000131607056},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5600000023841858},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5227000117301941},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4555000066757202},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.43790000677108765},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3837999999523163},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.3695000112056732},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.3578999936580658},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.30480000376701355},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.30070000886917114},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.2971999943256378},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2892000079154968},{"id":"https://openalex.org/C77304879","wikidata":"https://www.wikidata.org/wiki/Q211485","display_name":"Space technology","level":2,"score":0.2815000116825104},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.27799999713897705},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.27730000019073486},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2757999897003174},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.2556999921798706},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.2531000077724457},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.2508000135421753}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl68686.2025.00046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6271340847015381,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1970047515","https://openalex.org/W2023406772","https://openalex.org/W2345147456","https://openalex.org/W2418145342","https://openalex.org/W2544872163","https://openalex.org/W2969903328","https://openalex.org/W3003778129","https://openalex.org/W3005620031","https://openalex.org/W3035586868","https://openalex.org/W3113059441","https://openalex.org/W3141004699","https://openalex.org/W3158928873","https://openalex.org/W4225784788","https://openalex.org/W4313492219","https://openalex.org/W4386436139","https://openalex.org/W4387064010","https://openalex.org/W4401752539","https://openalex.org/W4402827382","https://openalex.org/W4406047295","https://openalex.org/W4406047665"],"related_works":[],"abstract_inverted_index":{"This":[0,171],"paper":[1],"presents":[2],"microarchitectural":[3],"and":[4,58,104,138,198],"physical":[5],"design":[6],"trade-offs":[7,96],"as":[8,10,108,186],"well":[9],"primitive":[11],"mapping":[12],"techniques":[13,21],"for":[14,176],"designing":[15],"high-throughput":[16],"area-efficient":[17],"RISC-V":[18,29,157],"soft-cores.":[19],"These":[20],"facilitate":[22],"the":[23,109,118,147,174],"implementation":[24,148],"of":[25,37,111,149,156],"tiny,":[26],"highly":[27],"efficient":[28],"cores":[30,158],"that":[31],"can":[32,159,188],"be":[33,160],"scaled":[34],"to":[35,131,145],"thousands":[36,155],"instances":[38],"on":[39,94,135,162,180],"large":[40,164],"FPGAs,":[41],"enabling":[42],"massively":[43],"parallel":[44],"overlays":[45,183],"by":[46],"pushing":[47],"above":[48],"<tex":[49,60,71],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[50,61,72],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\mathbf{1.":[51],"5}$</tex>":[52],"MIPS/LUT":[53,65],"in":[54,66,89,117,184],"a":[55,67,92,150,163,191],"single-core":[56],"setup":[57],"over":[59],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\mathbf{0.":[62],"8":[63],"1}$</tex>":[64],"kilo-core":[68,151],"configuration":[69],"delivering":[70],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\mathbf{5":[73],"1":[74],"2,":[75],"0":[76,77],"0}$</tex>":[78],"MIPS":[79],"peak":[80],"throughput.":[81,139],"The":[82,123],"proposed":[83],"fully":[84],"open-source":[85],"architecture":[86],"is":[87,128,143],"analyzed":[88],"detail,":[90],"with":[91],"focus":[93],"optimizing":[95],"between":[97,125],"core":[98],"pipeline":[99],"depth,":[100],"multithreading,":[101],"clock":[102,201],"speed,":[103],"configurable":[105],"parameters,":[106],"such":[107],"use":[110],"Digital":[112],"Signal":[113],"Processing":[114],"(DSP)":[115],"blocks":[116],"Arithmetic":[119],"Logic":[120],"Unit":[121],"(ALU).":[122],"interplay":[124],"these":[126],"parameters":[127],"carefully":[129],"examined":[130],"demonstrate":[132],"their":[133],"impact":[134],"system":[136],"scalability":[137],"A":[140],"case":[141],"study":[142],"presented":[144],"illustrate":[146],"system,":[152],"showing":[153],"how":[154],"deployed":[161],"FPGA":[165],"platform":[166],"while":[167],"maintaining":[168],"per-core":[169],"efficiency.":[170],"work":[172],"paves":[173],"way":[175],"scalable":[177],"many-core":[178],"designs":[179],"FPGAs":[181],"(and":[182],"general),":[185],"they":[187],"achieve":[189],"both":[190],"compact":[192],"area":[193],"footprint,":[194],"low":[195],"power":[196],"dissipation,":[197],"high":[199],"operating":[200],"speed.":[202]},"counts_by_year":[],"updated_date":"2026-03-28T06:11:35.319607","created_date":"2026-03-27T00:00:00"}
