{"id":"https://openalex.org/W7140645691","doi":"https://doi.org/10.1109/fpl68686.2025.00043","title":"Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs","display_name":"Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs","publication_year":2025,"publication_date":"2025-09-01","ids":{"openalex":"https://openalex.org/W7140645691","doi":"https://doi.org/10.1109/fpl68686.2025.00043"},"language":null,"primary_location":{"id":"doi:10.1109/fpl68686.2025.00043","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00043","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112508774","display_name":"Satwant Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Satwant Singh","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130635036","display_name":"Michael Schneider","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Schneider","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130671835","display_name":"Ziad Aboud","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ziad Aboud","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130682405","display_name":"Jonathan Peterson","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Peterson","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130649850","display_name":"Senani Gunaratna","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Senani Gunaratna","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130717189","display_name":"Ting Yew","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ting Yew","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130716983","display_name":"Cindy Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cindy Lee","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5130681727","display_name":"Rick Crotty","orcid":null},"institutions":[{"id":"https://openalex.org/I116921496","display_name":"Lattice Semiconductor (United States)","ror":"https://ror.org/01hght844","country_code":"US","type":"company","lineage":["https://openalex.org/I116921496"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rick Crotty","raw_affiliation_strings":["Lattice Semiconductor Corp,San Jose,CA,USA"],"affiliations":[{"raw_affiliation_string":"Lattice Semiconductor Corp,San Jose,CA,USA","institution_ids":["https://openalex.org/I116921496"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5112508774"],"corresponding_institution_ids":["https://openalex.org/I116921496"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6739463,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"254","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.36059999465942383,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.36059999465942383,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.20479999482631683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.10760000348091125,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5737000107765198},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4964999854564667},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4765999913215637},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42879998683929443},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4171000123023987}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6656000018119812},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5737000107765198},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4964999854564667},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4765999913215637},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4296000003814697},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42879998683929443},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4171000123023987},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32109999656677246},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2978000044822693},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.29429998993873596},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2892000079154968},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.27649998664855957}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl68686.2025.00043","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00043","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8224107027053833}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1554938446","https://openalex.org/W1965849649","https://openalex.org/W2007959382","https://openalex.org/W2013409221","https://openalex.org/W2017589892","https://openalex.org/W2023146792","https://openalex.org/W2097521167","https://openalex.org/W2113645429","https://openalex.org/W2113764809","https://openalex.org/W2125272903","https://openalex.org/W2127099598","https://openalex.org/W2137265220","https://openalex.org/W2148676074","https://openalex.org/W2163599210","https://openalex.org/W2171768221","https://openalex.org/W2762946676","https://openalex.org/W2789564496","https://openalex.org/W2918037051","https://openalex.org/W3008619650","https://openalex.org/W3130162703","https://openalex.org/W3132749493","https://openalex.org/W4205199457","https://openalex.org/W4393578439"],"related_works":[],"abstract_inverted_index":{"Power-efficient":[0],"mid-range":[1,33],"FPGAs":[2],"enhance":[3],"computational":[4],"capabilities,":[5],"reduce":[6],"system":[7,197],"size":[8,109,198],"and":[9,11,22,65,98,107,121,199,217],"weight,":[10],"extend":[12],"battery":[13],"life":[14],"in":[15,30,92,141,151,206,214,255,269,272,279],"power-sensitive":[16],"applications":[17],"such":[18],"as":[19,124,126,156],"autonomous":[20],"robots":[21],"AI-enabled":[23],"devices.":[24],"This":[25,267],"paper":[26],"presents":[27],"architectural":[28],"enhancements":[29,90],"Lattice":[31],"Avant":[32,208],"FPGAs,":[34],"manufactured":[35],"using":[36],"16":[37],"nm":[38],"FinFET":[39],"process":[40],"technology.":[41],"We":[42],"explore":[43],"the":[44,86,152,167,186,203,207,215,275,280,284],"benefits":[45],"of":[46,58,119,185,283],"Four-Input":[47],"Lookup":[48],"Tables":[49],"(LUT4s)":[50],"organized":[51],"into":[52,176],"Programmable":[53,76],"Function":[54],"Unit":[55],"(PFU)":[56],"clusters":[57],"12":[59,238],"LUT4s,":[60],"along":[61],"with":[62,71],"associated":[63],"registers":[64,213,258],"other":[66,105],"logic.":[67],"PFUs":[68],"are":[69,81],"coupled":[70],"optimized":[72],"routing":[73],"to":[74,84,104,165,233,261],"construct":[75],"Logic":[77],"Cells":[78],"(PLCs),":[79],"which":[80,113,210,249],"then":[82],"arrayed":[83],"form":[85],"FPGA":[87],"fabric.":[88],"These":[89],"result":[91],"reduced":[93],"area,":[94],"lower":[95],"static":[96],"power,":[97],"decreased":[99],"dynamic":[100,277],"power":[101,200,278],"consumption":[102],"compared":[103,232,260],"LUT":[106,120],"PFU":[108],"choices.":[110],"Our":[111],"analysis,":[112],"combines":[114],"published":[115],"benchmarks,":[116,128],"internal":[117,127],"analysis":[118],"PLC":[122,144,159,179,193],"areas,":[123],"well":[125],"indicates":[129],"that,":[130],"on":[131],"average,":[132],"users":[133],"will":[134],"have":[135],"about":[136],"30":[137],"%":[138,184,231],"LUT4s":[139],"leftover":[140],"a":[142,157,177,191,219,234,244,262],"LUT4-based":[143],"array":[145,148,160,180],"if":[146],"that":[147,161,236,243],"is":[149,242],"constructed":[150],"same":[153],"die":[154,187],"area":[155,188],"LUT6-based":[158,192],"was":[162],"large":[163],"enough":[164],"fit":[166,175],"original":[168],"design.":[169],"Alternatively,":[170],"an":[171],"average":[172],"design":[173],"can":[174],"LUT4":[178],"occupying":[181],"approximately":[182],"70":[183],"required":[189],"by":[190,229],"array,":[194],"thereby":[195],"reducing":[196],"consumption.":[201],"Additionally,":[202],"slice":[204,216,235],"clock":[205,221,227,276,285],"architecture,":[209],"serves":[211],"both":[212],"includes":[218],"per-slice":[220],"turnoff":[222],"feature,":[223],"reduces":[224],"total":[225,252],"register":[226],"toggles":[228],"43":[230],"has":[237,250],"registers.":[239],"The":[240],"reason":[241],"partially":[245,263],"used":[246,264],"smaller":[247],"slice,":[248],"fewer":[251,256],"registers,":[253],"results":[254],"unneeded":[257],"toggling":[259],"larger":[265],"slice.":[266],"reduction":[268],"unnecessary":[270],"toggles,":[271],"turn,":[273],"decreases":[274],"final":[281],"stage":[282],"distribution.":[286]},"counts_by_year":[],"updated_date":"2026-03-28T06:11:35.319607","created_date":"2026-03-27T00:00:00"}
