{"id":"https://openalex.org/W7140771247","doi":"https://doi.org/10.1109/fpl68686.2025.00023","title":"TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer","display_name":"TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer","publication_year":2025,"publication_date":"2025-09-01","ids":{"openalex":"https://openalex.org/W7140771247","doi":"https://doi.org/10.1109/fpl68686.2025.00023"},"language":null,"primary_location":{"id":"doi:10.1109/fpl68686.2025.00023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101545534","display_name":"Qin Luo","orcid":"https://orcid.org/0009-0002-2740-813X"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Qin Luo","raw_affiliation_strings":["The Chinese University of Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037988878","display_name":"Xinshi Zang","orcid":"https://orcid.org/0009-0002-7889-4481"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Xinshi Zang","raw_affiliation_strings":["The Chinese University of Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F.Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5121024072","display_name":"Martin D.F. Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I141568987","display_name":"Hong Kong Baptist University","ror":"https://ror.org/0145fw131","country_code":"HK","type":"education","lineage":["https://openalex.org/I141568987"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Martin D.F. Wong","raw_affiliation_strings":["Hong Kong Baptist University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hong Kong Baptist University","institution_ids":["https://openalex.org/I141568987"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101545534"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6376341,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"83","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7954000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7954000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.03999999910593033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.037700001150369644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5990999937057495},{"id":"https://openalex.org/keywords/reinforcement-learning","display_name":"Reinforcement learning","score":0.45559999346733093},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4133000075817108},{"id":"https://openalex.org/keywords/placer-mining","display_name":"Placer mining","score":0.3183000087738037},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.2973000109195709},{"id":"https://openalex.org/keywords/active-learning","display_name":"Active learning (machine learning)","score":0.28690001368522644}],"concepts":[{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5990999937057495},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5885999798774719},{"id":"https://openalex.org/C97541855","wikidata":"https://www.wikidata.org/wiki/Q830687","display_name":"Reinforcement learning","level":2,"score":0.45559999346733093},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4133000075817108},{"id":"https://openalex.org/C43592290","wikidata":"https://www.wikidata.org/wiki/Q12148490","display_name":"Placer mining","level":2,"score":0.3183000087738037},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2973000109195709},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.29019999504089355},{"id":"https://openalex.org/C77967617","wikidata":"https://www.wikidata.org/wiki/Q4677561","display_name":"Active learning (machine learning)","level":2,"score":0.28690001368522644},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2741999924182892},{"id":"https://openalex.org/C67203356","wikidata":"https://www.wikidata.org/wiki/Q1321905","display_name":"Reinforcement","level":2,"score":0.273499995470047},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2606000006198883},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2572999894618988},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.2526000142097473},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.251800000667572}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl68686.2025.00023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W2018721259","https://openalex.org/W2086835975","https://openalex.org/W2151758817","https://openalex.org/W2151812709","https://openalex.org/W2181150664","https://openalex.org/W2194775991","https://openalex.org/W2732589717","https://openalex.org/W2945592068","https://openalex.org/W3171752851","https://openalex.org/W3197603378","https://openalex.org/W3200609275","https://openalex.org/W4353031982","https://openalex.org/W4388079952","https://openalex.org/W4389166770","https://openalex.org/W4391455278","https://openalex.org/W4391612219","https://openalex.org/W4392693587","https://openalex.org/W4401414663","https://openalex.org/W4402195488","https://openalex.org/W4408151607","https://openalex.org/W7133209275","https://openalex.org/W7133217793"],"related_works":[],"abstract_inverted_index":{"Reinforcement":[0],"learning":[1],"(RL)-based":[2],"macro":[3,86,110],"placement":[4,87,153],"has":[5],"garnered":[6],"significant":[7],"interest":[8],"in":[9,43,68,111,128],"both":[10],"the":[11,44,48,55,93,105,112,116,129,134,138,143,163,171,181],"fields":[12],"of":[13,58,137],"artificial":[14],"intelligence":[15],"and":[16,31,46,73,158,169],"electronic":[17],"design":[18],"automation":[19],"(EDA),":[20],"due":[21],"to":[22,35,103,132,180],"its":[23],"excellent":[24],"potential":[25],"for":[26,64,89,108],"achieving":[27],"better":[28],"performance,":[29],"power":[30],"area":[32],"optimization":[33],"compared":[34,155,179],"analytical":[36],"methods.":[37],"However,":[38],"existing":[39],"techniques":[40],"are":[41],"restricted":[42],"ASIC":[45],"ignore":[47],"other":[49],"hardware":[50],"architectures":[51],"like":[52],"FPGA.":[53],"Neglecting":[54],"intrinsic":[56],"characters":[57],"FPGA":[59],"structures,":[60],"conventional":[61],"RL-based":[62,85],"methods":[63],"ASICs":[65],"may":[66],"result":[67],"a":[69,83,99,120],"large":[70],"exploration":[71,172],"space":[72],"low":[74],"sample":[75],"efficiency.":[76],"In":[77],"this":[78],"work,":[79],"we":[80,96],"propose":[81],"TRPlaceFPGA-MP,":[82],"two-stage":[84],"framework":[88],"Ultrascale":[90],"FPGAs.":[91],"Leveraging":[92],"columnar":[94],"architecture,":[95],"first":[97,113],"train":[98],"tiny":[100],"RL":[101,123,183],"model":[102,124],"determine":[104,133],"candidate":[106],"columns":[107],"each":[109],"stage.":[114],"With":[115],"pruned":[117],"searching":[118],"space,":[119],"more":[121],"sophisticated":[122],"is":[125],"then":[126],"trained":[127],"second":[130],"stage":[131],"ultimate":[135],"positions":[136],"macros.":[139],"Experimental":[140],"results":[141],"on":[142],"MLCAD2023":[144],"contest":[145],"benchmark":[146],"demonstrate":[147],"that":[148],"TRPlaceFPGA-MP":[149],"still":[150],"maintains":[151],"superior":[152],"performance":[154],"with":[156],"Vivado":[157],"DreamplaceFPGA-MP.":[159],"Furthermore,":[160],"it":[161],"improves":[162],"convergence":[164],"rate":[165],"by":[166,174],"2.28":[167],"x":[168],"accelerates":[170],"process":[173],"<tex":[175],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[176],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$1.61":[177],"x$</tex>":[178],"one-stage":[182],"approach.":[184]},"counts_by_year":[],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2026-03-27T00:00:00"}