{"id":"https://openalex.org/W7140830317","doi":"https://doi.org/10.1109/fpl68686.2025.00021","title":"URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage","display_name":"URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage","publication_year":2025,"publication_date":"2025-09-01","ids":{"openalex":"https://openalex.org/W7140830317","doi":"https://doi.org/10.1109/fpl68686.2025.00021"},"language":null,"primary_location":{"id":"doi:10.1109/fpl68686.2025.00021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060452626","display_name":"Martim Rosado","orcid":"https://orcid.org/0009-0002-2312-1991"},"institutions":[{"id":"https://openalex.org/I4210142272","display_name":"Center for Migration Studies of New York","ror":"https://ror.org/058zr4t24","country_code":"US","type":"education","lineage":["https://openalex.org/I4210142272"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Martim Rosado","raw_affiliation_strings":["On behalf of the CMS Collaboration"],"affiliations":[{"raw_affiliation_string":"On behalf of the CMS Collaboration","institution_ids":["https://openalex.org/I4210142272"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101912340","display_name":"Pedro R. Tomas","orcid":"https://orcid.org/0000-0001-7938-4972"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Pedro Tom\u00e1s","raw_affiliation_strings":["INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa,Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa,Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015710714","display_name":"Nuno Roma","orcid":"https://orcid.org/0000-0003-2491-4977"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Nuno Roma","raw_affiliation_strings":["INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa,Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa,Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5130665627","display_name":"Andr\u00e9 David","orcid":null},"institutions":[{"id":"https://openalex.org/I4210142272","display_name":"Center for Migration Studies of New York","ror":"https://ror.org/058zr4t24","country_code":"US","type":"education","lineage":["https://openalex.org/I4210142272"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 David","raw_affiliation_strings":["On behalf of the CMS Collaboration"],"affiliations":[{"raw_affiliation_string":"On behalf of the CMS Collaboration","institution_ids":["https://openalex.org/I4210142272"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5060452626"],"corresponding_institution_ids":["https://openalex.org/I4210142272"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.66195276,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"68","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.24560000002384186,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.24560000002384186,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.09849999845027924,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0860000029206276,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.5906999707221985},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5828999876976013},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5638999938964844},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5083000063896179},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.310699999332428},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.28349998593330383}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7272999882698059},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.5906999707221985},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5828999876976013},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5638999938964844},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5418000221252441},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5083000063896179},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4083000123500824},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.31630000472068787},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.310699999332428},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.28349998593330383},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2809999883174896},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2786000072956085},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2678000032901764},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.25850000977516174},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2583000063896179}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl68686.2025.00021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl68686.2025.00021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5722017288208008,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G5402566535","display_name":null,"funder_award_id":"2022.06780.PTDC,UIDB/50021/2020,PT/BD/154723/2022","funder_id":"https://openalex.org/F4320334779","funder_display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia"}],"funders":[{"id":"https://openalex.org/F4320334779","display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","ror":"https://ror.org/00snfqn58"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2025064965","https://openalex.org/W2126647846","https://openalex.org/W2151512268","https://openalex.org/W2971523937","https://openalex.org/W3034977853","https://openalex.org/W3048587899","https://openalex.org/W3081820378","https://openalex.org/W4225479915","https://openalex.org/W4286571643","https://openalex.org/W4361192114","https://openalex.org/W4387869744","https://openalex.org/W4389901936","https://openalex.org/W4406247692","https://openalex.org/W4408567632"],"related_works":[],"abstract_inverted_index":{"First-In":[0],"First-Out":[1],"(FIFO)":[2],"memories":[3],"are":[4,83],"essential":[5],"for":[6,48,72],"data":[7,37,88],"transfers":[8],"in":[9],"Field":[10],"Programmable":[11],"Gate":[12],"Array":[13],"(FPGA)":[14],"designs,":[15],"providing":[16],"buffering":[17],"and":[18,24,77,90],"communication":[19],"facilities":[20],"between":[21,124],"different":[22,92],"components":[23],"clock":[25,127],"domains.":[26],"Traditional":[27],"implementations":[28],"rely":[29],"on":[30,98],"Block-RAM":[31],"(BRAM)":[32],"cells,":[33],"but":[34],"transferring":[35],"large":[36,119],"packets":[38,117],"can":[39],"lead":[40],"to":[41,65,85,113],"excessive":[42],"BRAM":[43],"usage,":[44],"potentially":[45],"limiting":[46],"resources":[47],"other":[49],"parts":[50],"of":[51],"the":[52,67,109],"system.":[53],"This":[54],"paper":[55],"proposes":[56],"an":[57,99],"alternative":[58],"Ultra-RAM":[59],"(URAM)-based":[60],"asynchronous":[61],"FIFO":[62],"design,":[63],"allowing":[64],"optimise":[66],"overall":[68],"FPGA":[69,103],"RAM":[70],"usage":[71],"applications":[73],"that":[74],"require":[75],"deep":[76],"wide":[78],"FIFOs.":[79],"Several":[80],"implementation":[81],"strategies":[82],"explored":[84],"ensure":[86],"maximum":[87],"throughput":[89],"support":[91],"packet":[93],"sizes.":[94],"Experimental":[95],"results":[96],"obtained":[97],"AMD":[100],"Zynq":[101],"UltraScale+":[102],"running":[104],"at":[105],"500":[106],"MHz":[107],"demonstrate":[108],"proposed":[110],"FIFO's":[111],"ability":[112],"successfully":[114],"transfer":[115],"complete":[116],"(as":[118],"as":[120],"1024":[121],"64-bit":[122],"words)":[123],"two":[125],"distinct":[126],"domains":[128],"without":[129],"introducing":[130],"any":[131],"stalls.":[132]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2026-03-27T00:00:00"}
