{"id":"https://openalex.org/W2525265324","doi":"https://doi.org/10.1109/fpl.2016.7577348","title":"Fast and area efficient adder for wide data in recent Xilinx FPGAs","display_name":"Fast and area efficient adder for wide data in recent Xilinx FPGAs","publication_year":2016,"publication_date":"2016-08-01","ids":{"openalex":"https://openalex.org/W2525265324","doi":"https://doi.org/10.1109/fpl.2016.7577348","mag":"2525265324"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2016.7577348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2016.7577348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131088","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078608165","display_name":"Petter K\u00e4llstr\u00f6m","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Petter Kallstrom","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028423819","display_name":"Oscar Gustafsson","orcid":"https://orcid.org/0000-0003-3470-3911"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Oscar Gustafsson","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078608165"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.7351,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.75260826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9534914493560791},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8032108545303345},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.7739206552505493},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7397972941398621},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7257364988327026},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.568865180015564},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5683170557022095},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5018694400787354},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4902234673500061},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4737955927848816},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4626382887363434},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1770704984664917},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.06909570097923279}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9534914493560791},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8032108545303345},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.7739206552505493},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7397972941398621},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7257364988327026},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.568865180015564},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5683170557022095},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5018694400787354},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4902234673500061},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4737955927848816},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4626382887363434},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1770704984664917},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.06909570097923279},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2016.7577348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2016.7577348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:DiVA.org:liu-131088","is_oa":true,"landing_page_url":"http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131088","pdf_url":null,"source":{"id":"https://openalex.org/S4306401559","display_name":"KTH Publication Database DiVA (KTH Royal Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference paper"}],"best_oa_location":{"id":"pmh:oai:DiVA.org:liu-131088","is_oa":true,"landing_page_url":"http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131088","pdf_url":null,"source":{"id":"https://openalex.org/S4306401559","display_name":"KTH Publication Database DiVA (KTH Royal Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference paper"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1971632278","https://openalex.org/W2104203942","https://openalex.org/W2107713929","https://openalex.org/W2111568453","https://openalex.org/W2112969627","https://openalex.org/W2122910852","https://openalex.org/W2142727297","https://openalex.org/W2912759893","https://openalex.org/W2981356405","https://openalex.org/W6729420934"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W2064215635","https://openalex.org/W1971632278"],"abstract_inverted_index":{"Most":[0],"modern":[1],"FPGAs":[2,17],"have":[3,19],"very":[4],"optimised":[5],"carry":[6,13,47,62,72],"logic":[7],"for":[8,113],"efficient":[9],"implementations":[10],"of":[11],"ripple":[12],"adders":[14],"(RCA).":[15],"Some":[16],"also":[18],"a":[20,110],"six":[21],"input":[22],"look":[23],"up":[24],"table":[25],"(LUT)":[26],"per":[27,77],"cell,":[28,78],"whereof":[29],"two":[30,75],"inputs":[31],"are":[32],"used":[33],"during":[34],"normal":[35,98,111],"addition.":[36],"In":[37,87],"this":[38],"paper":[39],"we":[40],"present":[41],"an":[42],"architecture":[43],"that":[44,103],"compresses":[45],"the":[46,58,71,83,89,97,104],"chain":[48,73],"length":[49,115],"to":[50],"N/2":[51],"in":[52,74,120],"recent":[53],"Xilinx":[54],"FPGA,":[55],"by":[56,66],"utilising":[57],"LUTs":[59],"better.":[60],"This":[61],"compression":[63],"was":[64],"implemented":[65],"letting":[67],"some":[68,80],"cells":[69],"calculate":[70,82],"bits":[76,119],"while":[79],"others":[81],"summary":[84],"output":[85],"bits.":[86],"total":[88],"proposed":[90,105],"design":[91],"uses":[92],"no":[93],"more":[94],"hardware":[95],"than":[96,109,117],"adder.":[99],"The":[100],"result":[101],"shows":[102],"adder":[106,112],"is":[107],"faster":[108],"word":[114],"larger":[116],"64":[118],"Virtex-6":[121],"FPGAs.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-10-07T00:00:00"}