{"id":"https://openalex.org/W2527244689","doi":"https://doi.org/10.1109/fpl.2016.7577326","title":"The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer","display_name":"The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer","publication_year":2016,"publication_date":"2016-08-01","ids":{"openalex":"https://openalex.org/W2527244689","doi":"https://doi.org/10.1109/fpl.2016.7577326","mag":"2527244689"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2016.7577326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2016.7577326","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024675991","display_name":"Oleg Petelin","orcid":"https://orcid.org/0000-0002-8535-3432"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Oleg Petelin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024675991"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.9188,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.78254292,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7964670658111572},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6592794060707092},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6194316744804382},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6135416030883789},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5619555711746216},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.46615374088287354},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.42956048250198364},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3417212963104248},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3264957666397095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22583451867103577},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21131747961044312},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.177444189786911},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17588311433792114},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.15145465731620789}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7964670658111572},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6592794060707092},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6194316744804382},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6135416030883789},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5619555711746216},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.46615374088287354},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42956048250198364},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3417212963104248},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3264957666397095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22583451867103577},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21131747961044312},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.177444189786911},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17588311433792114},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.15145465731620789}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2016.7577326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2016.7577326","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1481987700","https://openalex.org/W1522950391","https://openalex.org/W1523051745","https://openalex.org/W1524957862","https://openalex.org/W1978599303","https://openalex.org/W2005602803","https://openalex.org/W2007049691","https://openalex.org/W2012602696","https://openalex.org/W2023146792","https://openalex.org/W2038318386","https://openalex.org/W2076729972","https://openalex.org/W2089710952","https://openalex.org/W2095258817","https://openalex.org/W2098557772","https://openalex.org/W2116094656","https://openalex.org/W2138840350","https://openalex.org/W2144853876","https://openalex.org/W2148676074","https://openalex.org/W2164340799","https://openalex.org/W2169788109","https://openalex.org/W6685041248","https://openalex.org/W7045235261"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2014709025","https://openalex.org/W2155019192","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2316202402","https://openalex.org/W2074043759","https://openalex.org/W3146360095","https://openalex.org/W2184011203"],"abstract_inverted_index":{"The":[0,147],"rapid":[1],"growth":[2],"of":[3,22,39,51,66,73],"wire":[4],"RC":[5],"delay":[6,95,155],"with":[7,161,172],"technology":[8],"scaling":[9],"has":[10],"put":[11],"increasing":[12],"pressure":[13],"on":[14,42,53,79,140],"FPGA":[15,33],"architects":[16],"to":[17,68,104,109,124,137,159,170],"make":[18],"more":[19],"efficient":[20],"use":[21,117],"the":[23,28,37,43,54,64,70,74,98,141,151,177],"different":[24,71],"layers":[25,46,72],"available":[26],"in":[27],"metal":[29,45,57,75,145],"stack.":[30],"While":[31],"commercial":[32],"architectures":[34,90,120,133,160,171],"have":[35,61],"implemented":[36],"majority":[38],"inter-logic-block":[40],"wiring":[41],"lower":[44],"and":[47,84,91,94,101,111,121,134,143,166],"a":[48],"small":[49],"fraction":[50],"wires":[52,139,175],"least-resistive":[55],"upper":[56],"layers,":[58],"published":[59],"explorations":[60],"largely":[62],"ignored":[63],"question":[65],"how":[67],"exploit":[69],"stack,":[76],"focusing":[77],"instead":[78],"very":[80],"simple":[81],"interconnect":[82,114,127],"topologies":[83,136,149],"physical":[85],"models.":[86],"We":[87,116],"generate":[88],"VPR":[89,105,179],"detailed":[92],"area":[93],"models":[96],"at":[97],"22nm":[99],"node":[100],"present":[102],"enhancements":[103,123],"that":[106],"enable":[107],"us":[108],"describe":[110],"evaluate":[112],"complex":[113,126],"topologies.":[115],"our":[118],"new":[119],"tool":[122],"explore":[125],"patterns":[128],"suitable":[129],"for":[130],"modern":[131],"unidirectional":[132],"suggest":[135],"connect":[138],"semi-global":[142],"global":[144,163,173],"layers.":[146],"proposed":[148],"improve":[150],"critical":[152],"path":[153],"routing":[154],"by":[156,167],"17%":[157],"compared":[158,169],"no":[162],"layer":[164,174],"wires,":[165],"5-13%":[168],"using":[176],"default":[178],"switch":[180],"pattern.":[181]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
