{"id":"https://openalex.org/W1670230100","doi":"https://doi.org/10.1109/fpl.2015.7294014","title":"A technology mapper for depth-constrained FPGA logic cells","display_name":"A technology mapper for depth-constrained FPGA logic cells","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1670230100","doi":"https://doi.org/10.1109/fpl.2015.7294014","mag":"1670230100"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7294014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294014","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/handle/20.500.14299/194145","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048586562","display_name":"Zhenghong Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210110458","display_name":"Institute of Electronics","ror":"https://ror.org/01z143507","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210110458"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhenghong Jiang","raw_affiliation_strings":["System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210110458","https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028606671","display_name":"Grace Zgheib","orcid":"https://orcid.org/0000-0002-1476-2984"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Grace Zgheib","raw_affiliation_strings":["Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005352722","display_name":"Colin Yu Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110458","display_name":"Institute of Electronics","ror":"https://ror.org/01z143507","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210110458"]},{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Colin Yu Lin","raw_affiliation_strings":["System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210110458","https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102760981","display_name":"David Novo","orcid":"https://orcid.org/0000-0002-5510-4152"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"David Novo","raw_affiliation_strings":["Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102845279","display_name":"Zhihong Huang","orcid":"https://orcid.org/0000-0002-4235-2587"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210110458","display_name":"Institute of Electronics","ror":"https://ror.org/01z143507","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210110458"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihong Huang","raw_affiliation_strings":["System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210110458","https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101808217","display_name":"Liqun Yang","orcid":"https://orcid.org/0000-0003-4391-6396"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210110458","display_name":"Institute of Electronics","ror":"https://ror.org/01z143507","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210110458"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liqun Yang","raw_affiliation_strings":["System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210110458","https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087392088","display_name":"Haigang Yang","orcid":"https://orcid.org/0000-0002-6471-9730"},"institutions":[{"id":"https://openalex.org/I4210110458","display_name":"Institute of Electronics","ror":"https://ror.org/01z143507","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210110458"]},{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haigang Yang","raw_affiliation_strings":["System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department Institute of Electronics, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210110458","https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020575991","display_name":"Paolo Ienne","orcid":"https://orcid.org/0000-0002-6142-7345"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Paolo Ienne","raw_affiliation_strings":["Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), School of Computer and Communication Sciences, 1015, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5048586562"],"corresponding_institution_ids":["https://openalex.org/I19820366","https://openalex.org/I4210110458"],"apc_list":null,"apc_paid":null,"fwci":0.1973,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.56668739,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7331117987632751},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6410375237464905},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5945273637771606},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5868276357650757},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.5174692273139954},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5167959928512573},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5072667002677917},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.48664793372154236},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4158360958099365},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4150574505329132},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.4132072925567627},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.41011151671409607},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4069902002811432},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.40556299686431885},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38910937309265137},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.35828858613967896},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.30108642578125},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2373647391796112},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12358224391937256},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11632359027862549},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09304240345954895}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7331117987632751},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6410375237464905},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5945273637771606},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5868276357650757},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.5174692273139954},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5167959928512573},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5072667002677917},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.48664793372154236},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4158360958099365},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4150574505329132},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.4132072925567627},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.41011151671409607},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4069902002811432},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.40556299686431885},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38910937309265137},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.35828858613967896},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.30108642578125},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2373647391796112},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12358224391937256},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11632359027862549},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09304240345954895},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2015.7294014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294014","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:299654","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/194145","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:299654","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/194145","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5199999809265137,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2005602803","https://openalex.org/W2034565294","https://openalex.org/W2082947990","https://openalex.org/W2091956800","https://openalex.org/W2100465945","https://openalex.org/W2100955320","https://openalex.org/W2104451751","https://openalex.org/W2126814059","https://openalex.org/W2133287836","https://openalex.org/W2140975144","https://openalex.org/W2150787480","https://openalex.org/W2155316178","https://openalex.org/W4239323126"],"related_works":["https://openalex.org/W2053477566","https://openalex.org/W1966764473","https://openalex.org/W2197466303","https://openalex.org/W2139569078","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W2359075490","https://openalex.org/W4379115868","https://openalex.org/W2170504327"],"abstract_inverted_index":{"In":[0],"the":[1,22,45,48,52,125,165,198,201,224],"last":[2],"decade,":[3],"progress":[4],"in":[5,21,51,70,80,143,175,187,212],"logic":[6,54,77,112,128,137,146],"synthesis":[7,71],"has":[8,66],"brought":[9],"about":[10],"new":[11,29,76,97,177],"advantageous":[12],"circuit":[13,49],"representations.":[14],"These":[15],"representations,":[16],"such":[17,191],"as":[18],"And-Inverter":[19],"Graphs":[20],"ubiquitous":[23],"open-source":[24],"synthesizer":[25],"ABC,":[26],"have":[27,119],"inspired":[28],"designs":[30],"of":[31,39,47,131,134,145,200,229],"Field":[32],"Programmable":[33],"Gate":[34],"Arrays":[35],"(FPGAs),":[36],"which,":[37],"instead":[38],"using":[40],"Look-Up":[41],"Tables":[42],"(LUTs),":[43],"mimic":[44],"topology":[46],"representation":[50,64],"basic":[53],"cells.":[55,78],"More":[56],"recent":[57],"examples":[58],"are":[59,108,141,151],"Majority-Inverter":[60],"Graphs,":[61],"another":[62],"uniform":[63,132],"which":[65,73],"triggered":[67],"considerable":[68],"interest":[69],"and":[72,118,148,158],"naturally":[74],"suggests":[75],"Yet,":[79],"this":[81],"paper":[82],"we":[83,195,207],"observe":[84],"how":[85],"na\u00efvely":[86],"adapting":[87],"technology":[88],"mapping":[89],"solutions":[90,160],"for":[91,189],"classic":[92],"LUT-based":[93],"FPGAs":[94],"to":[95,161],"these":[96,163,176],"architectures":[98],"incurs":[99],"severe":[100],"shortcomings.":[101],"The":[102],"key":[103],"issue":[104],"is":[105,116,167,185],"that":[106],"LUTs":[107],"inherently":[109],"input-constrained":[110],"(the":[111],"function":[113,138],"they":[114],"implement":[115],"irrelevant)":[117],"generally":[120],"a":[121,168,179,209],"single":[122],"output;":[123],"on":[124,203],"other":[126],"hand,":[127],"cells":[129],"made":[130],"networks":[133],"some":[135],"fundamental":[136],"(e.g.,":[139],"And-Invert)":[140],"constrained":[142],"terms":[144],"depth":[147],"multiple":[149],"outputs":[150],"an":[152],"integral":[153],"feature.":[154],"We":[155],"introduce":[156],"novel":[157],"effective":[159],"address":[162],"differences;":[164],"result":[166],"highly":[169],"versatile":[170],"mapper\u2014thus":[171],"enabling":[172],"further":[173],"research":[174],"architectures\u2014with":[178],"significantly":[180],"better":[181],"performance":[182],"than":[183],"what":[184],"described":[186],"literature":[188],"one":[190,204],"architecture.":[192],"Specifically,":[193],"when":[194],"compare":[196],"with":[197],"state":[199],"art":[202],"sample":[205],"architecture,":[206],"obtain":[208],"significant":[210],"decrease":[211],"area":[213],"(on":[214],"average":[215],"18%":[216],"over":[217],"several":[218],"benchmarks)":[219],"while":[220],"also":[221],"improving":[222],"slightly":[223],"critical":[225],"path":[226],"(a":[227],"reduction":[228],"3%).":[230]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}