{"id":"https://openalex.org/W1673751684","doi":"https://doi.org/10.1109/fpl.2015.7294010","title":"Estimating circuit delays in FPGAs after technology mapping","display_name":"Estimating circuit delays in FPGAs after technology mapping","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1673751684","doi":"https://doi.org/10.1109/fpl.2015.7294010","mag":"1673751684"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7294010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://biblio.ugent.be/publication/7177837/file/7177920.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008546367","display_name":"Berg Severens","orcid":null},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Berg Severens","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Belgium","Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073897749","display_name":"Elias Vansteenkiste","orcid":null},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Elias Vansteenkiste","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Belgium","Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020622964","display_name":"Karel Heyse","orcid":null},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Karel Heyse","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Belgium","Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["Department of Electronics and Information Systems, Ghent University, Belgium","Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Hardware and Embedded Systems Team, Computer Systems Lab, Department of Electronics and Information Systems, Ghent University, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I32597200"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9205582141876221},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.77158123254776},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.7702516913414001},{"id":"https://openalex.org/keywords/identification","display_name":"Identification (biology)","score":0.6569613814353943},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5341977477073669},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4940965473651886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49242815375328064},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4356182813644409},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4130093455314636},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.37184518575668335},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35548490285873413},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34773024916648865},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08939915895462036}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9205582141876221},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.77158123254776},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.7702516913414001},{"id":"https://openalex.org/C116834253","wikidata":"https://www.wikidata.org/wiki/Q2039217","display_name":"Identification (biology)","level":2,"score":0.6569613814353943},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5341977477073669},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4940965473651886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49242815375328064},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4356182813644409},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4130093455314636},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37184518575668335},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35548490285873413},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34773024916648865},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08939915895462036},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C59822182","wikidata":"https://www.wikidata.org/wiki/Q441","display_name":"Botany","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2015.7294010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:archive.ugent.be:7177837","is_oa":true,"landing_page_url":"http://hdl.handle.net/1854/LU-7177837","pdf_url":"https://biblio.ugent.be/publication/7177837/file/7177920.pdf","source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9780993428005","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:archive.ugent.be:7177837","is_oa":true,"landing_page_url":"http://hdl.handle.net/1854/LU-7177837","pdf_url":"https://biblio.ugent.be/publication/7177837/file/7177920.pdf","source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9780993428005","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1673751684.pdf","grobid_xml":"https://content.openalex.org/works/W1673751684.grobid-xml"},"referenced_works_count":8,"referenced_works":["https://openalex.org/W1998292918","https://openalex.org/W2010394621","https://openalex.org/W2049823658","https://openalex.org/W2063781085","https://openalex.org/W2075137913","https://openalex.org/W2123980833","https://openalex.org/W2138383740","https://openalex.org/W2164340799"],"related_works":["https://openalex.org/W3147061323","https://openalex.org/W2118796996","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2365114398","https://openalex.org/W2243815476","https://openalex.org/W2789349722","https://openalex.org/W3128899411","https://openalex.org/W1985308002","https://openalex.org/W2614722573"],"abstract_inverted_index":{"An":[0],"FPGA":[1,13,32,47,167],"implementation":[2],"requires":[3],"a":[4,92,131,154],"significant":[5],"effort":[6],"of":[7,28,38,62,78,94,134,166],"the":[8,31,36,39,42,46,52,60,79,119,135,138,142,164],"hardware":[9],"designer,":[10],"who":[11],"optimizes":[12],"designs":[14],"by":[15],"going":[16],"through":[17],"many":[18],"time-consuming":[19],"CAD":[20],"flow":[21],"iterations.":[22],"These":[23],"iterations":[24],"provide":[25,130,150],"two":[26],"types":[27],"feedback:":[29],"(1)":[30],"performance":[33,74,96],"and":[34,65,76,104,113],"(2)":[35],"identification":[37,77,133],"parts":[40,136],"having":[41,137],"highest":[43,139],"impact":[44,140],"on":[45,51,141],"performance.":[48,143],"Both":[49],"depend":[50],"wirelength":[53],"behavior.":[54],"Studies":[55],"have":[56],"been":[57],"dedicated":[58],"to":[59,70,110],"estimation":[61,97],"local":[63],"[5]":[64],"global":[66],"[4]":[67],"wirelengths,":[68],"but":[69],"our":[71],"knowledge":[72],"both":[73],"estimations":[75],"critical":[80,120],"zone":[81,121],"are":[82,122],"not":[83],"present":[84],"in":[85],"literature.":[86],"Therefore":[87],"this":[88],"paper,":[89],"firstly,":[90],"presents":[91],"comparison":[93],"three":[95],"techniques:":[98],"logic":[99],"depth,":[100],"Monte":[101,127,147],"Carlo":[102,128,148],"simulation":[103],"fast":[105],"placement":[106],"(ordered":[107],"from":[108],"low":[109],"high":[111],"accuracy":[112],"runtime).":[114],"Secondly,":[115],"four":[116],"methods":[117],"identifying":[118],"compared.":[123],"Results":[124],"show":[125],"that":[126,146],"simulations":[129,149],"good":[132],"We":[144],"conclude":[145],"useful":[151],"feedback":[152],"within":[153],"short":[155],"runtime":[156],"(about":[157],"30":[158],"times":[159],"faster":[160],"than":[161],"placement),":[162],"reducing":[163],"time-to-market":[165],"implementations.":[168]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
