{"id":"https://openalex.org/W1669973258","doi":"https://doi.org/10.1109/fpl.2015.7294008","title":"Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks","display_name":"Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1669973258","doi":"https://doi.org/10.1109/fpl.2015.7294008","mag":"1669973258"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7294008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024675991","display_name":"Oleg Petelin","orcid":"https://orcid.org/0000-0002-8535-3432"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Oleg Petelin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024675991"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.2002,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.57269642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.779376745223999},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7384576797485352},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6645269393920898},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6448058485984802},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6239337921142578},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5479294657707214},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.45218178629875183},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4506056308746338},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.4491729736328125},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4488074779510498},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44869425892829895},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4291457235813141},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3743327260017395},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20637136697769165}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.779376745223999},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7384576797485352},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6645269393920898},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6448058485984802},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6239337921142578},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5479294657707214},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.45218178629875183},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4506056308746338},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.4491729736328125},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4488074779510498},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44869425892829895},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4291457235813141},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3743327260017395},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20637136697769165},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2015.7294008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1522950391","https://openalex.org/W1523051745","https://openalex.org/W1524957862","https://openalex.org/W2005602803","https://openalex.org/W2014091871","https://openalex.org/W2023146792","https://openalex.org/W2076729972","https://openalex.org/W2098557772","https://openalex.org/W2102503881","https://openalex.org/W2110265185","https://openalex.org/W2115826669","https://openalex.org/W2138840350","https://openalex.org/W2144853876","https://openalex.org/W2161640626","https://openalex.org/W2296084214","https://openalex.org/W7045235261"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2743305891","https://openalex.org/W4385309418","https://openalex.org/W2331259470","https://openalex.org/W2742852324","https://openalex.org/W2019954703","https://openalex.org/W2535520145"],"abstract_inverted_index":{"FPGA":[0],"routing":[1,5,115,128,137],"architectures":[2,24,74,97],"consist":[3],"of":[4,17,37,43,72,96,101,135,163],"wires":[6],"and":[7,21,60,141,156,165],"programmable":[8],"switches":[9],"which":[10,68],"together":[11],"account":[12],"for":[13,92,160],"a":[14,30,35,45,56,63,93,161],"significant":[15],"portion":[16],"the":[18,41,77,99,113,127,133,175],"fabric":[19],"delay":[20],"area.":[22],"Routing":[23],"have":[25],"traditionally":[26],"been":[27],"evaluated":[28],"using":[29],"full":[31,176],"CAD":[32,50,178],"flow":[33,46,179],"with":[34,171],"suite":[36],"benchmark":[38,102],"circuits.":[39,103],"While":[40],"results":[42,173],"such":[44],"can":[47,61],"be":[48],"accurate,":[49],"tools":[51],"are":[52],"often":[53],"tuned":[54],"to":[55,66,112,146],"specific":[57],"architecture":[58],"type":[59],"take":[62],"long":[64],"time":[65],"run":[67],"prohibits":[69],"quick":[70],"exploration":[71],"different":[73,138],"early":[75],"in":[76,180],"design":[78],"process.":[79],"In":[80],"this":[81],"paper":[82],"we":[83,131,143],"present":[84,157],"an":[85,148],"alternative":[86],"approach":[87],"that":[88],"quickly":[89],"estimates":[90,120,159],"routability":[91,106,150,158,172],"wide":[94],"range":[95,162],"without":[98],"use":[100],"Our":[104],"new":[105],"predictor":[107,155],"first":[108],"assigns":[109],"congestion":[110],"probabilities":[111,134],"architecture's":[114],"resources":[116],"based":[117],"on":[118],"demand":[119],"found":[121],"via":[122],"efficient":[123],"path":[124],"enumeration":[125],"through":[126],"graph.":[129],"Next,":[130],"compute":[132],"successfully":[136],"source/sink":[139],"connections":[140],"finally":[142],"combine":[144],"them":[145],"assign":[147],"overall":[149],"score.":[151],"We":[152],"describe":[153],"our":[154],"6-LUT":[164],"4-LUT":[166],"architectures,":[167],"showing":[168],"reasonable":[169],"agreement":[170],"from":[174],"VPR":[177],"much":[181],"less":[182],"CPU":[183],"time.":[184]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}