{"id":"https://openalex.org/W1676776177","doi":"https://doi.org/10.1109/fpl.2015.7294005","title":"Fast FPGA system for microarchitecture optimization on synthesizable modern processor design","display_name":"Fast FPGA system for microarchitecture optimization on synthesizable modern processor design","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1676776177","doi":"https://doi.org/10.1109/fpl.2015.7294005","mag":"1676776177"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7294005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069512300","display_name":"Libo Huang","orcid":"https://orcid.org/0000-0002-8307-6742"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Libo Huang","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070632746","display_name":"Yongwen Wang","orcid":"https://orcid.org/0009-0008-2514-2052"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongwen Wang","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103276566","display_name":"Qiang Dou","orcid":"https://orcid.org/0000-0003-2320-8413"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Dou","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101949780","display_name":"Chengyi Zhang","orcid":"https://orcid.org/0009-0001-1966-0776"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chengyi Zhang","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100518680","display_name":"Caixia Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Caixia Sun","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101720578","display_name":"Chao Xu","orcid":"https://orcid.org/0000-0003-0514-3070"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chao Xu","raw_affiliation_strings":["School of Computer, National University of Defense Technology, Changsha, P.R. China","School of Computer National University of Defense Technology Changsha 410073 China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer, National University of Defense Technology, Changsha, P.R. China","institution_ids":["https://openalex.org/I170215575"]},{"raw_affiliation_string":"School of Computer National University of Defense Technology Changsha 410073 China","institution_ids":["https://openalex.org/I170215575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04274611,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"57","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7785506844520569},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.7514438629150391},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.743574857711792},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.5886727571487427},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5792193412780762},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4835819602012634},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.47184017300605774},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4518049955368042},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.414654403924942},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3821265995502472},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36908257007598877}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7785506844520569},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.7514438629150391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.743574857711792},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.5886727571487427},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5792193412780762},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4835819602012634},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.47184017300605774},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4518049955368042},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.414654403924942},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3821265995502472},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36908257007598877},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2015.7294005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320324150","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1970900297","https://openalex.org/W1985938075","https://openalex.org/W2022807575","https://openalex.org/W2030959856","https://openalex.org/W2032699516","https://openalex.org/W2038769854","https://openalex.org/W2078376517","https://openalex.org/W2093994565","https://openalex.org/W4243872270"],"related_works":["https://openalex.org/W4230568114","https://openalex.org/W1538545038","https://openalex.org/W2972412786","https://openalex.org/W2168654016","https://openalex.org/W1995348478","https://openalex.org/W2121435882","https://openalex.org/W3099493149","https://openalex.org/W2072783274","https://openalex.org/W3157702025","https://openalex.org/W2463263055"],"abstract_inverted_index":{"Microarchitecture":[0],"optimization":[1,98],"for":[2,41],"processor":[3,74,82,128],"design":[4,93],"is":[5,46,76,117],"a":[6,47,65,71,110,125],"must":[7],"to":[8,78,102],"achieve":[9,79],"target":[10],"system":[11,122],"performance.":[12],"Provided":[13],"the":[14,57,60,104,118,137],"register":[15],"transfer":[16],"level":[17],"(RTL)":[18],"model":[19],"in":[20],"real":[21,138],"chip":[22],"design,":[23],"this":[24],"paper":[25],"proposes":[26],"MOFPGA":[27,63,116],"system,":[28],"which":[29],"uses":[30],"field":[31],"programmable":[32],"gate":[33],"array":[34],"(FPGA)":[35],"prototyping":[36],"as":[37,90],"an":[38],"effective":[39],"method":[40],"fine-grain":[42],"microarchitecture":[43],"optimization.":[44],"It":[45],"fast,":[48],"reconfigurable,":[49],"and":[50,75,94,134],"visible":[51],"platform":[52,68],"with":[53,70],"zero":[54],"impact":[55],"on":[56],"performance":[58,106],"of":[59,107],"monitored":[61],"processor.":[62],"implements":[64,124],"complete":[66],"computing":[67],"equipped":[69],"modern":[72,126],"out-of-order":[73,127],"able":[77],"60":[80],"MHz":[81],"frequency.":[83],"Besides":[84],"general":[85],"FPGA":[86,105,121],"implementation":[87],"techniques":[88],"such":[89,109,131],"multi-port":[91],"SRAM":[92],"gate-clock":[95],"conversion,":[96],"extensive":[97],"efforts":[99],"are":[100],"done":[101],"improve":[103],"mapping":[108],"large":[111],"core.":[112],"To":[113],"our":[114],"knowledge,":[115],"first":[119],"published":[120],"that":[123],"running":[129],"at":[130],"high":[132],"frequency":[133],"can":[135],"report":[136],"SPEC":[139],"CPU2000":[140],"evaluation":[141],"results.":[142]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}