{"id":"https://openalex.org/W1663248305","doi":"https://doi.org/10.1109/fpl.2015.7294000","title":"UniStream: A unified stream architecture combining configuration and data processing","display_name":"UniStream: A unified stream architecture combining configuration and data processing","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1663248305","doi":"https://doi.org/10.1109/fpl.2015.7294000","mag":"1663248305"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7294000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100369172","display_name":"Jian Yan","orcid":"https://orcid.org/0000-0001-5400-4611"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jian Yan","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048136162","display_name":"Jifang Jin","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jifang Jin","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100346968","display_name":"Ying Wang","orcid":"https://orcid.org/0000-0001-5623-4605"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ying Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103281733","display_name":"Xuegong Zhou","orcid":"https://orcid.org/0000-0003-4178-4094"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuegong Zhou","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107994859","display_name":"Philip H. W. Leong","orcid":"https://orcid.org/0000-0002-3923-3499"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Philip Leong","raw_affiliation_strings":["School of Electrical and Information Engineering, The University of Sydney, Australia","School of Electrical and Information Engineering, The University of Sydney, Room 852, Electrical Engineering Building J03, Australia"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, The University of Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]},{"raw_affiliation_string":"School of Electrical and Information Engineering, The University of Sydney, Room 852, Electrical Engineering Building J03, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, No. 825 Zhangheng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100369172"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.323,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57339822,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.9355809688568115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8095231056213379},{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.8021470308303833},{"id":"https://openalex.org/keywords/data-stream","display_name":"Data stream","score":0.6517389416694641},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6174874305725098},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5418683886528015},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5013208389282227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4357868432998657},{"id":"https://openalex.org/keywords/data-stream-mining","display_name":"Data stream mining","score":0.4152848422527313},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3677141070365906},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3590434491634369},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.32633140683174133},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2908423840999603},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.20743870735168457},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09062585234642029},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08720257878303528}],"concepts":[{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.9355809688568115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8095231056213379},{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.8021470308303833},{"id":"https://openalex.org/C2778484313","wikidata":"https://www.wikidata.org/wiki/Q1172540","display_name":"Data stream","level":2,"score":0.6517389416694641},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6174874305725098},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5418683886528015},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5013208389282227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4357868432998657},{"id":"https://openalex.org/C89198739","wikidata":"https://www.wikidata.org/wiki/Q3079880","display_name":"Data stream mining","level":2,"score":0.4152848422527313},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3677141070365906},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3590434491634369},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.32633140683174133},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2908423840999603},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.20743870735168457},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09062585234642029},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08720257878303528},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2015.7294000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7294000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1994652506","https://openalex.org/W2000036939","https://openalex.org/W2018817973","https://openalex.org/W2018873598","https://openalex.org/W2031384549","https://openalex.org/W2081381252","https://openalex.org/W2091338501","https://openalex.org/W2147676121","https://openalex.org/W2151471392","https://openalex.org/W2154363663","https://openalex.org/W2158203472","https://openalex.org/W2170920195","https://openalex.org/W3151593078","https://openalex.org/W4299566147","https://openalex.org/W6844603724"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W1587494897","https://openalex.org/W2169674017","https://openalex.org/W2385174725","https://openalex.org/W2188443807","https://openalex.org/W1497726515","https://openalex.org/W2770508556","https://openalex.org/W2129487136","https://openalex.org/W4389449520","https://openalex.org/W180351855"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"UniStream,":[3],"a":[4],"unified":[5,23],"stream":[6,11,19,33,39,52,59,110],"architecture":[7],"based":[8],"on":[9,50,83,91],"point-to-point":[10],"channels":[12],"combining":[13],"both":[14],"bitstream":[15,29,92],"configuration":[16,30,56],"and":[17,31,57,76,86,97],"data":[18,32,58,95],"processing.":[20],"In":[21],"addition,":[22],"APIs":[24],"are":[25,81],"provided":[26],"to":[27],"support":[28],"processing,":[34],"as":[35,37],"well":[36],"the":[38,48,51,69],"interconnect.":[40],"A":[41],"cost":[42],"model":[43],"is":[44],"also":[45],"presented":[46],"for":[47],"overhead":[49],"interconnect,":[53],"hardware":[54],"task":[55],"processing":[60],"at":[61],"system":[62],"level,":[63],"which":[64],"can":[65,104],"be":[66,105],"used":[67],"during":[68],"early":[70],"stage":[71],"of":[72,79],"development.":[73],"The":[74],"flexibility":[75],"high":[77],"efficiency":[78],"UniStream":[80],"demonstrated":[82],"Xilinx":[84],"Virtex-5":[85],"Virtex-6":[87],"FPGAs.":[88],"Experimental":[89],"results":[90],"configuration/":[93],"read-back,":[94],"encryption/decryption":[96],"Discrete":[98],"Cosine":[99],"Transformation":[100],"show":[101],"that":[102],"performance":[103],"significantly":[106],"improved":[107],"with":[108],"different":[109],"modes.":[111]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
