{"id":"https://openalex.org/W1610902723","doi":"https://doi.org/10.1109/fpl.2015.7293986","title":"Serial and parallel interleaved modular multipliers on FPGA platform","display_name":"Serial and parallel interleaved modular multipliers on FPGA platform","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1610902723","doi":"https://doi.org/10.1109/fpl.2015.7293986","mag":"1610902723"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7293986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293986","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018296502","display_name":"Khalid Javeed","orcid":"https://orcid.org/0000-0003-4645-4043"},"institutions":[{"id":"https://openalex.org/I42934936","display_name":"Dublin City University","ror":"https://ror.org/04a1a1e81","country_code":"IE","type":"education","lineage":["https://openalex.org/I42934936"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Khalid Javeed","raw_affiliation_strings":["School of Electronics Engineering, Dublin City University, Dublin, Ireland","School of Electronics Engineering, Dublin City University, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Dublin City University, Dublin, Ireland","institution_ids":["https://openalex.org/I42934936"]},{"raw_affiliation_string":"School of Electronics Engineering, Dublin City University, Ireland","institution_ids":["https://openalex.org/I42934936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036477576","display_name":"Xiaojun Wang","orcid":"https://orcid.org/0000-0002-4674-7711"},"institutions":[{"id":"https://openalex.org/I42934936","display_name":"Dublin City University","ror":"https://ror.org/04a1a1e81","country_code":"IE","type":"education","lineage":["https://openalex.org/I42934936"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Xiaojun Wang","raw_affiliation_strings":["School of Electronics Engineering, Dublin City University, Dublin, Ireland","School of Electronics Engineering, Dublin City University, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Dublin City University, Dublin, Ireland","institution_ids":["https://openalex.org/I42934936"]},{"raw_affiliation_string":"School of Electronics Engineering, Dublin City University, Ireland","institution_ids":["https://openalex.org/I42934936"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111581819","display_name":"Mike Scott","orcid":null},"institutions":[{"id":"https://openalex.org/I4210098195","display_name":"CertiRx (United States)","ror":"https://ror.org/00eykv937","country_code":"US","type":"company","lineage":["https://openalex.org/I4210098195"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike Scott","raw_affiliation_strings":["CertiVox, UK, United Kingdom","CertiVox UK, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CertiVox, UK, United Kingdom","institution_ids":["https://openalex.org/I4210098195"]},{"raw_affiliation_string":"CertiVox UK, United Kingdom","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":10.7194,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.97965197,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6577771902084351},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6238172054290771},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6226390600204468},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.560773491859436},{"id":"https://openalex.org/keywords/modular-exponentiation","display_name":"Modular exponentiation","score":0.5400292873382568},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5331724286079407},{"id":"https://openalex.org/keywords/modular-arithmetic","display_name":"Modular arithmetic","score":0.5163305997848511},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4965205788612366},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4810809791088104},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3662005364894867},{"id":"https://openalex.org/keywords/public-key-cryptography","display_name":"Public-key cryptography","score":0.3011817932128906},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2524884343147278},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.11988621950149536}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6577771902084351},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6238172054290771},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6226390600204468},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.560773491859436},{"id":"https://openalex.org/C152763109","wikidata":"https://www.wikidata.org/wiki/Q1228841","display_name":"Modular exponentiation","level":4,"score":0.5400292873382568},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5331724286079407},{"id":"https://openalex.org/C32049820","wikidata":"https://www.wikidata.org/wiki/Q319400","display_name":"Modular arithmetic","level":3,"score":0.5163305997848511},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4965205788612366},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4810809791088104},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3662005364894867},{"id":"https://openalex.org/C203062551","wikidata":"https://www.wikidata.org/wiki/Q201339","display_name":"Public-key cryptography","level":3,"score":0.3011817932128906},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2524884343147278},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.11988621950149536},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2015.7293986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293986","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320838","display_name":"Higher Education Authority","ror":"https://ror.org/0471xye93"},{"id":"https://openalex.org/F4320332178","display_name":"National Institute of Standards and Technology","ror":"https://ror.org/05xpvk416"},{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W127770406","https://openalex.org/W1499231268","https://openalex.org/W1968556724","https://openalex.org/W1972461879","https://openalex.org/W2063884927","https://openalex.org/W2090911915","https://openalex.org/W2096133993","https://openalex.org/W2097848615","https://openalex.org/W2107953479","https://openalex.org/W2134012933","https://openalex.org/W2137153089","https://openalex.org/W2149087966","https://openalex.org/W2153253155","https://openalex.org/W2164774316","https://openalex.org/W4237773356","https://openalex.org/W4246892041"],"related_works":["https://openalex.org/W3182915524","https://openalex.org/W2285294304","https://openalex.org/W1995898468","https://openalex.org/W2364059967","https://openalex.org/W2610264794","https://openalex.org/W2055766186","https://openalex.org/W2039465140","https://openalex.org/W2238095429","https://openalex.org/W3046800386","https://openalex.org/W2013253681"],"abstract_inverted_index":{"Modular":[0],"multiplication":[1,39,112,169],"is":[2],"a":[3,68,73,109],"core":[4],"operation":[5],"in":[6,55,65,89,113,170],"all":[7],"public":[8],"key":[9],"based":[10,36],"cryptosystems.":[11],"The":[12,84,104,123,137],"performance":[13],"of":[14],"these":[15,162],"cryptosystems":[16],"can":[17],"be":[18],"enhanced":[19],"substantially":[20],"by":[21],"incorporating":[22],"an":[23],"optimized":[24],"modular":[25,34,50,70,111,144,168],"multiplier.":[26],"This":[27],"paper":[28],"presents":[29],"serial":[30,47,81,105,155],"and":[31,41,92,118,132,148,156],"parallel":[32,69,124,142,158],"radix-4":[33,48,106,125,143],"multipliers":[35],"on":[37],"interleaved":[38,49,82],"algorithm":[40],"Montgomery":[42],"power":[43],"laddering":[44],"technique.":[45],"A":[46],"multiplier":[51,71,107,126,145],"provides":[52,146],"50%":[53],"reduction":[54,64],"the":[56,63,79,141,152],"required":[57],"clock":[58,66],"cycles.":[59],"In":[60],"addition":[61],"to":[62,78,166],"cycles,":[67],"maintains":[72],"critical":[74],"path":[75],"delay":[76],"comparable":[77],"bit":[80,154,157],"multipliers.":[83],"proposed":[85],"designs":[86,163],"are":[87,164],"implemented":[88],"Verilog":[90],"HDL":[91],"synthesized":[93],"targeting":[94],"virtex-6":[95],"FPGA":[96],"platform":[97],"using":[98],"Xilinx":[99],"ISE":[100],"14.2":[101],"Design":[102],"suite.":[103],"computes":[108],"256-bit":[110],"1.3\u03bcs,":[114],"occupies":[115,129],"3.9K":[116],"LUTs,":[117,131],"runs":[119,133],"at":[120,134],"96":[121],"MHz.":[122,136],"takes":[127],"0.77\u03bcs,":[128],"5.3K":[130],"166":[135],"results":[138],"show":[139],"that":[140],"62%":[147],"49%":[149],"speed-up":[150],"over":[151],"corresponding":[153],"versions,":[159],"respectively.":[160],"Thus,":[161],"suitable":[165],"accelerate":[167],"many":[171],"cryptographic":[172],"processors.":[173]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":7}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
