{"id":"https://openalex.org/W1621597718","doi":"https://doi.org/10.1109/fpl.2015.7293980","title":"An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs","display_name":"An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1621597718","doi":"https://doi.org/10.1109/fpl.2015.7293980","mag":"1621597718"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7293980","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293980","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053452059","display_name":"Roel C. A. Oomen","orcid":"https://orcid.org/0009-0009-4324-4068"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Roel Oomen","raw_affiliation_strings":["State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100665213","display_name":"Tuan Anh Nguyen","orcid":"https://orcid.org/0000-0003-3558-2154"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tuan Nguyen","raw_affiliation_strings":["Woodruff School of Mechanical Engineering, Huazhong University of Science and Technology, Wuhan, GA, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Woodruff School of Mechanical Engineering, Huazhong University of Science and Technology, Wuhan, GA, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081768631","display_name":"Henk Corporaal","orcid":"https://orcid.org/0000-0003-4506-5732"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Henk Corporaal","raw_affiliation_strings":["State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"7439","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9201278686523438},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7329410314559937},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5502330660820007},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39498287439346313},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3947141766548157},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33520442247390747}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9201278686523438},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7329410314559937},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5502330660820007},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39498287439346313},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3947141766548157},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33520442247390747}],"mesh":[],"locations_count":8,"locations":[{"id":"doi:10.1109/fpl.2015.7293980","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293980","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/3ed977de-6207-4585-be47-3691ebf9dc4b","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/3ed977de-6207-4585-be47-3691ebf9dc4b","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Oomen, R, Nguyen, T, Kumar, A & Corporaal, H 2015, An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs. in 25th International Conference on Field Programmable Logic and Applications, FPL 2015., 7293980, Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4, 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, 2/09/15. https://doi.org/10.1109/FPL.2015.7293980","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:867696","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=867696","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:880451","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=880451","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:library.tue.nl:867696","is_oa":false,"landing_page_url":"http://repository.tue.nl/867696","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:library.tue.nl:880451","is_oa":false,"landing_page_url":"http://repository.tue.nl/880451","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:pure.tue.nl:publications/3ed977de-6207-4585-be47-3691ebf9dc4b","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=84962396721&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Oomen, R, Nguyen, T, Kumar, A & Corporaal, H 2015, An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs. in 25th International Conference on Field Programmable Logic and Applications, FPL 2015., 7293980, Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4, 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, 2/09/15. https://doi.org/10.1109/FPL.2015.7293980","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:tue:oai:pure.tue.nl:publications/3ed977de-6207-4585-be47-3691ebf9dc4b","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/3ed977de-6207-4585-be47-3691ebf9dc4b","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"25th International Conference on Field Programmable Logic and Applications, FPL 2015, 1 - 4","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W309055912","https://openalex.org/W1983517606","https://openalex.org/W2039535443","https://openalex.org/W2059722306","https://openalex.org/W2075397577","https://openalex.org/W2106767353","https://openalex.org/W2129487136","https://openalex.org/W2145520491","https://openalex.org/W2153197578","https://openalex.org/W2171549192","https://openalex.org/W2183064252","https://openalex.org/W2489262679","https://openalex.org/W6669387963"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Partial":[0],"reconfiguration":[1],"is":[2,94,118,189],"a":[3,126,139,180],"technique":[4,182],"used":[5],"to":[6,70,108,137,142,159,163,183],"increase":[7],"the":[8,18,23,26,30,53,72,87,112,122,133,165,168],"flexibility":[9],"of":[10,17,25,55,68,80,99,111,132],"an":[11],"FPGA-based":[12],"system":[13,19,50],"by":[14,34],"reprogramming":[15],"parts":[16],"dynamically":[20],"without":[21],"interrupting":[22],"operation":[24],"other":[27],"modules.":[28],"Despite":[29],"runtime":[31],"benefits":[32],"offered":[33],"partially":[35],"reconfigurable":[36,56],"(PR)":[37],"systems,":[38],"creating":[39],"and":[40,59,82,92,150,170],"storing":[41],"partial":[42],"bitstreams":[43],"(PBs)":[44],"are":[45,135],"becoming":[46],"major":[47],"concerns":[48],"for":[49,74,148,192],"architects":[51],"when":[52,86],"numbers":[54],"partitions":[57],"(RPs)":[58],"PR":[60,75],"modules":[61],"(PRMs)":[62],"increase.":[63],"It":[64],"takes":[65],"significant":[66],"amount":[67],"time":[69],"generate":[71],"PBs":[73,98,147],"systems":[76],"with":[77],"large":[78,151],"number":[79],"RPs":[81,93,155],"PRMs.":[83],"More":[84],"importantly,":[85],"mapping":[88],"relationship":[89],"between":[90],"PRMs":[91,152],"many-to-many,":[95],"several":[96],"almost-identical":[97],"one":[100],"PRM":[101],"must":[102],"be":[103],"stored":[104],"separately":[105],"which":[106],"leads":[107],"inefficient":[109],"utilization":[110],"memory":[113],"storage.":[114],"Therefore,":[115],"bitstream":[116],"relocation":[117],"drawing":[119],"interests":[120],"from":[121,167],"research":[123],"community":[124],"as":[125],"viable":[127],"solution.":[128],"Yet":[129],"almost":[130],"none":[131],"works":[134],"able":[136],"demonstrate":[138],"coherent":[140],"method":[141,188],"not":[143],"only":[144],"create":[145],"relocatable":[146],"complex":[149],"in":[153],"variable-size":[154],"but":[156],"also":[157],"how":[158],"do":[160],"that":[161,185],"automatically":[162],"free":[164],"designer":[166],"tedious":[169],"error":[171],"prone":[172],"manual":[173],"processes.":[174],"In":[175],"this":[176],"paper,":[177],"we":[178],"propose":[179],"new":[181],"fill":[184],"gap.":[186],"The":[187],"successfully":[190],"developed":[191],"Xilinx":[193],"Virtex":[194],"7":[195],"devices":[196],"using":[197],"Vivado":[198],"design":[199],"tool":[200],"flow.":[201]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
