{"id":"https://openalex.org/W1626377047","doi":"https://doi.org/10.1109/fpl.2015.7293953","title":"An efficient reconfigurable architecture by characterizing most frequent logic functions","display_name":"An efficient reconfigurable architecture by characterizing most frequent logic functions","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W1626377047","doi":"https://doi.org/10.1109/fpl.2015.7293953","mag":"1626377047"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2015.7293953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020554086","display_name":"Iman Ahmadpour","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Iman Ahmadpour","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran","Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060490428","display_name":"Behnam Khaleghi","orcid":"https://orcid.org/0000-0002-3655-0501"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Behnam Khaleghi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran","Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088069234","display_name":"Hossein Asadi","orcid":"https://orcid.org/0000-0002-0264-3865"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Hossein Asadi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran","Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I133529467"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.708914041519165},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6482454538345337},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.641363799571991},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6026495695114136},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6020311713218689},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5369638204574585},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5266594290733337},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5139769911766052},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5045255422592163},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4916704297065735},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4876040518283844},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4757625460624695},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4015846848487854},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38839125633239746},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3333357572555542},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.328685998916626},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23629212379455566},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19350922107696533},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08312326669692993}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.708914041519165},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6482454538345337},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.641363799571991},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6026495695114136},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6020311713218689},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5369638204574585},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5266594290733337},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5139769911766052},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5045255422592163},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4916704297065735},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4876040518283844},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4757625460624695},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4015846848487854},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38839125633239746},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3333357572555542},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.328685998916626},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23629212379455566},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19350922107696533},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08312326669692993},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2015.7293953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2015.7293953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W24683316","https://openalex.org/W564382181","https://openalex.org/W1990992881","https://openalex.org/W2005602803","https://openalex.org/W2018062740","https://openalex.org/W2072249022","https://openalex.org/W2102047509","https://openalex.org/W2113645429","https://openalex.org/W2120569261","https://openalex.org/W2133287836","https://openalex.org/W2133743520","https://openalex.org/W2141086131","https://openalex.org/W3143008962","https://openalex.org/W6648078114"],"related_works":["https://openalex.org/W2994343469","https://openalex.org/W1905312773","https://openalex.org/W1966764473","https://openalex.org/W2053477566","https://openalex.org/W2139569078","https://openalex.org/W2197466303","https://openalex.org/W4379115868","https://openalex.org/W4252227487","https://openalex.org/W2170504327","https://openalex.org/W2034419237"],"abstract_inverted_index":{"Generous":[0],"flexibility":[1],"of":[2,42,64],"Look-Up":[3],"Tables":[4],"(LUTs)":[5],"in":[6,56],"implementing":[7],"arbitrary":[8],"functions":[9,55,77],"comes":[10],"with":[11,18],"significant":[12],"performance":[13,157],"and":[14,59,109,137,143,160,166],"area":[15,151],"overheads":[16,30],"compared":[17,140,163],"their":[19],"Application-Specific":[20],"Integrated":[21],"Circuit":[22],"(ASIC)":[23],"equivalent.":[24],"One":[25],"approach":[26],"to":[27,32,39,85,91,116,141,164],"alleviate":[28],"such":[29],"is":[31],"use":[33],"less":[34],"flexible":[35],"logic":[36,43,68,119],"elements":[37],"capable":[38],"implement":[40],"majority":[41],"functions.":[44,104],"In":[45],"this":[46],"paper,":[47],"we":[48,81],"first":[49],"investigate":[50],"the":[51,94,129,149],"most":[52],"frequently":[53],"used":[54],"standard":[57],"benchmarks":[58,126],"then":[60],"design":[61,96],"a":[62,110],"set":[63],"less-flexible":[65],"but":[66],"area-efficient":[67],"cells,":[69],"called":[70],"Hard":[71],"Logics":[72],"(HL).":[73],"Since":[74],"higher":[75],"input":[76,103],"have":[78],"diverse":[79],"classes,":[80],"leverage":[82],"Shannon":[83],"decomposition":[84],"break":[86],"them":[87],"into":[88],"smaller":[89],"ones":[90],"either":[92],"reduce":[93],"HL":[95],"space":[97],"complexity":[98],"or":[99],"attain":[100,117],"asymmetric":[101],"low":[102],"A":[105],"heterogeneous":[106],"LUT-HL":[107],"architecture":[108,131,155],"mapping":[111],"scheme":[112],"are":[113],"also":[114],"proposed":[115,130,154],"maximum":[118],"resource":[120],"usage.":[121],"Experimental":[122],"results":[123],"on":[124],"MCNC":[125],"demonstrate":[127],"that":[128],"reduces":[132],"area-delay":[133],"product":[134],"by":[135,158],"13%":[136],"36%":[138],"as":[139,162],"LUT4":[142,165],"LUT6":[144,167],"based":[145,168],"FPGAs,":[146],"respectively.":[147],"Considering":[148],"same":[150],"budget,":[152],"our":[153],"improves":[156],"17%":[159],"2%":[161],"FPGAs.":[169]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}