{"id":"https://openalex.org/W2072367650","doi":"https://doi.org/10.1109/fpl.2014.6927498","title":"Effective FPGA debug for high-level synthesis generated circuits","display_name":"Effective FPGA debug for high-level synthesis generated circuits","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2072367650","doi":"https://doi.org/10.1109/fpl.2014.6927498","mag":"2072367650"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006132600","display_name":"Jeffrey Goeders","orcid":"https://orcid.org/0000-0002-9822-6926"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jeffrey Goeders","raw_affiliation_strings":["The University of British Columbia Faculty of Medicine, Vancouver, BC, CA","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of British Columbia Faculty of Medicine, Vancouver, BC, CA","institution_ids":[]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J.E. Wilton","raw_affiliation_strings":["The University of British Columbia Faculty of Medicine, Vancouver, BC, CA","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of British Columbia Faculty of Medicine, Vancouver, BC, CA","institution_ids":[]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":5.4414,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.96720089,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.9104064702987671},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7665377855300903},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7278770208358765},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7189909219741821},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6784998178482056},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5287781953811646},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.49945569038391113},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48093360662460327},{"id":"https://openalex.org/keywords/source-code","display_name":"Source code","score":0.43556880950927734},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4283847212791443},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.42329877614974976},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29343000054359436},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19334793090820312},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.08792468905448914}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.9104064702987671},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7665377855300903},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7278770208358765},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7189909219741821},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6784998178482056},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5287781953811646},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.49945569038391113},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48093360662460327},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.43556880950927734},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4283847212791443},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.42329877614974976},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29343000054359436},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19334793090820312},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.08792468905448914}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2014.6927498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W93786577","https://openalex.org/W572026064","https://openalex.org/W1805018943","https://openalex.org/W1965210897","https://openalex.org/W1970032753","https://openalex.org/W1994052066","https://openalex.org/W2057807751","https://openalex.org/W2071754498","https://openalex.org/W2075160498","https://openalex.org/W2088256110","https://openalex.org/W2097306889","https://openalex.org/W2101740426","https://openalex.org/W2105993342","https://openalex.org/W2107662612","https://openalex.org/W2112423443","https://openalex.org/W2113717210","https://openalex.org/W2120263045","https://openalex.org/W2121851099","https://openalex.org/W2130934470","https://openalex.org/W2148960378","https://openalex.org/W2153185479","https://openalex.org/W2159381165","https://openalex.org/W2162925013","https://openalex.org/W2168098726","https://openalex.org/W3145813894","https://openalex.org/W4246166885","https://openalex.org/W6675325827","https://openalex.org/W6676052100"],"related_works":["https://openalex.org/W2361273971","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2385068581","https://openalex.org/W2381166695","https://openalex.org/W4241045879","https://openalex.org/W2366346238","https://openalex.org/W2388687068","https://openalex.org/W2366922255","https://openalex.org/W2387706296"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"promises":[3],"to":[4,25,34,68],"increase":[5],"designer":[6],"productivity":[7],"in":[8],"the":[9,18,27,38,71,76,87,92],"face":[10],"of":[11,20,29,40,78],"steadily":[12],"increasing":[13],"FPGA":[14],"sizes,":[15],"and":[16,81],"broaden":[17],"market":[19],"use,":[21],"allowing":[22],"software":[23,79],"designers":[24,46,85],"reap":[26],"benefits":[28],"hardware":[30,84],"implementation.":[31],"One":[32],"roadblock":[33],"HLS":[35],"adoption":[36],"is":[37,67,74],"lack":[39],"a":[41,53],"debugging":[42],"infrastructure.":[43],"To":[44],"debug,":[45],"can":[47],"run":[48],"their":[49],"source":[50,94],"code":[51],"on":[52],"processor;":[54],"however,":[55],"this":[56],"does":[57],"not":[58,90],"capture":[59],"interactions":[60],"with":[61],"other":[62],"system":[63],"components.":[64],"The":[65],"alternative":[66],"debug":[69],"using":[70],"RTL,":[72],"which":[73],"beyond":[75],"expertise":[77],"designers,":[80],"impractical":[82],"for":[83],"as":[86],"RTL":[88],"may":[89],"resemble":[91],"original":[93],"code.":[95]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":11},{"year":2015,"cited_by_count":10}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
