{"id":"https://openalex.org/W2039535443","doi":"https://doi.org/10.1109/fpl.2014.6927480","title":"Portable module relocation and bitstream compression for Xilinx FPGAs","display_name":"Portable module relocation and bitstream compression for Xilinx FPGAs","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2039535443","doi":"https://doi.org/10.1109/fpl.2014.6927480","mag":"2039535443"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927480","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927480","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018892773","display_name":"Christian Beckhoff","orcid":null},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"Christian Beckhoff","raw_affiliation_strings":["University of Oslo, Norway","University of Oslo , Norway"],"affiliations":[{"raw_affiliation_string":"University of Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"University of Oslo , Norway","institution_ids":["https://openalex.org/I184942183"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064000482","display_name":"Dirk Koch","orcid":"https://orcid.org/0000-0002-2568-4432"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"Dirk Koch","raw_affiliation_strings":["University of Oslo, Norway","The University of Manchester; U.K"],"affiliations":[{"raw_affiliation_string":"University of Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"The University of Manchester; U.K","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071144214","display_name":"Jim T\u00f8rresen","orcid":"https://orcid.org/0000-0003-0556-0288"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"Jim Torresen","raw_affiliation_strings":["University of Oslo, Norway","University of Oslo , Norway"],"affiliations":[{"raw_affiliation_string":"University of Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"University of Oslo , Norway","institution_ids":["https://openalex.org/I184942183"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5018892773"],"corresponding_institution_ids":["https://openalex.org/I184942183"],"apc_list":null,"apc_paid":null,"fwci":2.4518,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.89036722,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.9613983631134033},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8719819784164429},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7885448336601257},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.756557822227478},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6452140212059021},{"id":"https://openalex.org/keywords/relocation","display_name":"Relocation","score":0.5803887248039246},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4983940124511719},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.4747612476348877},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.16366291046142578},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1570860743522644},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06884106993675232}],"concepts":[{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.9613983631134033},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8719819784164429},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7885448336601257},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.756557822227478},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6452140212059021},{"id":"https://openalex.org/C2779019381","wikidata":"https://www.wikidata.org/wiki/Q3499564","display_name":"Relocation","level":2,"score":0.5803887248039246},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4983940124511719},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4747612476348877},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.16366291046142578},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1570860743522644},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06884106993675232}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpl.2014.6927480","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927480","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/45c0517c-cbf8-46ee-8e36-a385efb49687","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/45c0517c-cbf8-46ee-8e36-a385efb49687","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Koch, D, Herkersdorf, A (ed.), Wehn, N (ed.) & Hubner, M (ed.) 2014, Portable module relocation and bitstream compression for Xilinx FPGAs. in A Herkersdorf, N Wehn & M Hubner (eds), Proceedings of the 24th International Conference on Field Programmable Logic and Applications. IEEE, USA, pp. 1-8, Field Programmable Logic and Applications (FPL), Munich, 2/09/14. https://doi.org/10.1109/FPL.2014.6927480","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.atira.dk:publications/45c0517c-cbf8-46ee-8e36-a385efb49687","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/portable-module-relocation-and-bitstream-compression-for-xilinx-fpgas(45c0517c-cbf8-46ee-8e36-a385efb49687).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Koch, D, Herkersdorf, A (ed.), Wehn, N (ed.) & Hubner, M (ed.) 2014, Portable module relocation and bitstream compression for Xilinx FPGAs. in A Herkersdorf, N Wehn & M Hubner (eds), Proceedings of the 24th International Conference on Field Programmable Logic and Applications. IEEE, USA, pp. 1-8, Field Programmable Logic and Applications (FPL), Munich, 2/09/14. https://doi.org/10.1109/FPL.2014.6927480","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323299","display_name":"Norges Forskningsr\u00e5d","ror":"https://ror.org/00epmv149"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W10022138","https://openalex.org/W1608570110","https://openalex.org/W1970616362","https://openalex.org/W1982031977","https://openalex.org/W1984105700","https://openalex.org/W2014254210","https://openalex.org/W2017492515","https://openalex.org/W2022126655","https://openalex.org/W2082507415","https://openalex.org/W2101906611","https://openalex.org/W2106767353","https://openalex.org/W2115133259","https://openalex.org/W2117513278","https://openalex.org/W2131595909","https://openalex.org/W2132588280","https://openalex.org/W2154363663","https://openalex.org/W2157367913","https://openalex.org/W2159959433","https://openalex.org/W2160274482","https://openalex.org/W2183064252","https://openalex.org/W6600404762","https://openalex.org/W6639785900","https://openalex.org/W6679634845","https://openalex.org/W6683359209","https://openalex.org/W6686206303"],"related_works":["https://openalex.org/W2399954712","https://openalex.org/W2901561495","https://openalex.org/W634170220","https://openalex.org/W2100981069","https://openalex.org/W3127136358","https://openalex.org/W2119281701","https://openalex.org/W2040087757","https://openalex.org/W2966803159","https://openalex.org/W3217667592","https://openalex.org/W2039535443"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,55,89],"novel":[4],"methodology":[5,26],"for":[6,12,27,83],"generating":[7],"and":[8,30,41,68,109],"compressing":[9],"configuration":[10,73,92],"bitstreams":[11,60],"modules":[13],"that":[14,106],"can":[15,79,113],"be":[16,81,114],"executed":[17],"at":[18,116],"different":[19],"positions":[20,87],"of":[21,37,45,54,65,72],"an":[22],"FPGA.":[23],"The":[24,51],"presented":[25],"bitstream":[28,39],"generation":[29],"compression":[31],"does":[32],"not":[33],"need":[34],"deep":[35],"knowledge":[36],"the":[38,46,84],"format":[40],"it":[42],"is":[43],"independent":[44,70],"target":[47],"(Xilinx)":[48],"FPGA":[49],"family.":[50],"approach":[52],"consists":[53],"design":[56],"phase":[57],"where":[58],"partial":[59,111],"are":[61],"decomposed":[62],"into":[63],"sequences":[64],"module":[66,69,107],"dependent":[67],"pieces":[71],"data.":[74],"At":[75],"run-time,":[76],"this":[77],"data":[78],"then":[80],"recomposed":[82],"individual":[85],"placement":[86],"by":[88],"special":[90],"DMA":[91],"controller":[93],"as":[94],"one":[95],"atomic":[96],"operation":[97],"without":[98],"any":[99],"further":[100],"software":[101],"interaction.":[102],"Our":[103],"experiments":[104],"demonstrate":[105],"relocation":[108],"fast":[110],"reconfiguration":[112],"implemented":[115],"low":[117],"logic":[118],"cost.":[119]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}