{"id":"https://openalex.org/W2037128610","doi":"https://doi.org/10.1109/fpl.2014.6927470","title":"Exploring architecture parameters for dual-output LUT based FPGAs","display_name":"Exploring architecture parameters for dual-output LUT based FPGAs","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2037128610","doi":"https://doi.org/10.1109/fpl.2014.6927470","mag":"2037128610"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927470","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048586562","display_name":"Zhenghong Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhenghong Jiang","raw_affiliation_strings":["University of Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210165038"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007933442","display_name":"Colin Yu Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Colin Yu Lin","raw_affiliation_strings":["System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059905480","display_name":"Liqun Yang","orcid":"https://orcid.org/0000-0002-3786-8458"},"institutions":[{"id":"https://openalex.org/I4210165038","display_name":"University of Chinese Academy of Sciences","ror":"https://ror.org/05qbk4x57","country_code":"CN","type":"education","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210165038"]},{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liqun Yang","raw_affiliation_strings":["University of Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210165038"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100455959","display_name":"Fei Wang","orcid":"https://orcid.org/0000-0003-3475-1163"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fei Wang","raw_affiliation_strings":["System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087392088","display_name":"Haigang Yang","orcid":"https://orcid.org/0000-0002-6471-9730"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haigang Yang","raw_affiliation_strings":["System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#"],"affiliations":[{"raw_affiliation_string":"System on Programmable Chip Research Department, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing, China#TAB#","institution_ids":["https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5048586562"],"corresponding_institution_ids":["https://openalex.org/I19820366","https://openalex.org/I4210165038"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.58795809,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7815390825271606},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.693607747554779},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6586750149726868},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5727829933166504},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5485131144523621},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.513083815574646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4338313043117523},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36405324935913086},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10878634452819824}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7815390825271606},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.693607747554779},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6586750149726868},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5727829933166504},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5485131144523621},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.513083815574646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4338313043117523},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36405324935913086},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10878634452819824},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2014.6927470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927470","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1528837436","https://openalex.org/W2091956800","https://openalex.org/W2113645429","https://openalex.org/W2113764809","https://openalex.org/W2116094656","https://openalex.org/W2138383740","https://openalex.org/W2155033206","https://openalex.org/W2159190350"],"related_works":["https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2131696304","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2125609625"],"abstract_inverted_index":{"Dual-output":[0],"lookup":[1],"tables":[2],"(LUTs)":[3],"are":[4],"mainstream":[5],"in":[6],"the":[7,37,53,61,68,152],"design":[8],"of":[9,16,19,55,57,87,105,117,133],"commercial":[10],"FPGA":[11,97],"products.":[12],"A":[13],"detailed":[14],"exploration":[15],"architectural":[17],"parameters":[18],"FPGAs":[20],"based":[21,32,159],"on":[22,52,60],"dualoutput":[23],"LUTs":[24],"is":[25,39,108],"presented.":[26],"Different":[27],"from":[28,138],"traditional":[29],"single-output":[30],"LUT":[31,79,115,131,158],"architecture,":[33],"\u201cshared":[34],"inputs\u201d":[35],"between":[36,76,147],"sub-LUTs":[38],"a":[40,74,96,101,113,130,135,143],"new":[41],"parameter":[42],"specific":[43],"to":[44,140],"dual-output":[45,157],"architecture.":[46],"In":[47],"this":[48],"paper,":[49],"we":[50,66,127],"focus":[51],"effect":[54],"ratio":[56,104,146],"shared":[58,88,102,121,144],"inputs":[59,71,122],"performance":[62],"and":[63,72,81,100,142,149],"area-efficiency.":[64],"First,":[65],"study":[67],"required":[69],"cluster":[70,77,82,136],"derive":[73],"relationship":[75],"inputs,":[78],"size":[80,83,116,132,137],"under":[84],"different":[85],"ratios":[86],"inputs.":[89],"Secondly,":[90],"our":[91],"evaluation":[92],"results":[93],"show":[94],"that":[95,129],"with":[98,119],"4-LUTs":[99],"input":[103,145],"two":[106],"thirds":[107],"preferred":[109],"for":[110,156],"area-efficiency,":[111],"while":[112],"large":[114],"9":[118],"no":[120],"achieves":[123],"best":[124,153],"performance.":[125],"Finally,":[126],"determine":[128],"4,":[134],"3":[139],"8,":[141],"1/3":[148],"2/3,":[150],"provide":[151],"area-delay":[154],"product":[155],"FPGAs.":[160]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
