{"id":"https://openalex.org/W2075329791","doi":"https://doi.org/10.1109/fpl.2014.6927456","title":"Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays","display_name":"Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2075329791","doi":"https://doi.org/10.1109/fpl.2014.6927456","mag":"2075329791"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061846371","display_name":"Davor Capalija","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Davor Capalija","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, ON, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, ON, Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080157948","display_name":"Tarek S. Abdelrahman","orcid":"https://orcid.org/0000-0002-2985-4873"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tarek S. Abdelrahman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, ON, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, ON, Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2776,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.83165404,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"7","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tile","display_name":"Tile","score":0.7987630367279053},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.7345334887504578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7210917472839355},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7035737037658691},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4362345337867737},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4219011664390564},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3312162756919861},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29576003551483154},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.08735600113868713}],"concepts":[{"id":"https://openalex.org/C2780728851","wikidata":"https://www.wikidata.org/wiki/Q468402","display_name":"Tile","level":2,"score":0.7987630367279053},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.7345334887504578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7210917472839355},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7035737037658691},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4362345337867737},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4219011664390564},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3312162756919861},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29576003551483154},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.08735600113868713},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2014.6927456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W46841846","https://openalex.org/W1549080799","https://openalex.org/W1966195532","https://openalex.org/W1979128269","https://openalex.org/W1987163471","https://openalex.org/W1988766139","https://openalex.org/W2008531154","https://openalex.org/W2015734495","https://openalex.org/W2029247336","https://openalex.org/W2034729118","https://openalex.org/W2045044674","https://openalex.org/W2046004968","https://openalex.org/W2051392577","https://openalex.org/W2052930524","https://openalex.org/W2062616902","https://openalex.org/W2070215512","https://openalex.org/W2085189212","https://openalex.org/W2102325484","https://openalex.org/W2104869032","https://openalex.org/W2111034061","https://openalex.org/W2114820519","https://openalex.org/W2120785033","https://openalex.org/W2121303892","https://openalex.org/W2128492110","https://openalex.org/W2130193491","https://openalex.org/W2140752352","https://openalex.org/W2144073284","https://openalex.org/W2144199167","https://openalex.org/W2151758817","https://openalex.org/W2160126455","https://openalex.org/W2161057695","https://openalex.org/W2180598069","https://openalex.org/W2554510265","https://openalex.org/W6645041241"],"related_works":["https://openalex.org/W2114959296","https://openalex.org/W38346124","https://openalex.org/W2502442966","https://openalex.org/W2138666621","https://openalex.org/W2383936314","https://openalex.org/W1992771654","https://openalex.org/W2022661278","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Mesh-of-functional-units":[0],"(mesh-of-FUs)":[1],"overlays":[2,38],"can":[3,133,171,179,184],"deliver":[4],"high-performance":[5],"because":[6],"they":[7,44],"expose":[8],"the":[9,16,66,78,91,148],"massively":[10],"parallel":[11,212],"FPGA":[12,40],"fabric":[13,41],"and":[14,51,73,88],"have":[15],"ability":[17],"to":[18,30,39,53,93,113,147],"be":[19,134,180],"customized":[20],"for":[21,122],"different":[22],"applications.":[23],"However,":[24],"a":[25,33,59,94,120,129,139,173,186,192,202],"key":[26],"challenge":[27],"is":[28,102],"how":[29],"quickly":[31],"compile":[32],"number":[34],"of":[35,71,84,100,141,175,188],"custom":[36],"mesh-of-FUs":[37],"such":[42],"that":[43,64,115,145,161,178],"achieve":[45],"high":[46],"f":[47,123,157],"<sub":[48,124,158],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[49,125,159],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">MAX</sub>":[50,126,160],"scale":[52],"large":[54],"mesh":[55],"sizes.":[56],"We":[57],"propose":[58],"tile-based":[60],"bottom-up":[61,152],"CAD":[62],"flow":[63,76,153,170,206],"utilizes":[65],"hierarchical":[67],"physical":[68],"design":[69],"techniques":[70],"partitioning":[72],"floorplanning.":[74],"Our":[75],"partitions":[77],"overlay":[79,86,132,166,194,204],"circuit":[80],"into":[81,191],"tiles,":[82],"groups":[83],"adjacent":[85],"cells,":[87],"then":[89],"compiles":[90],"tiles":[92,101,177,190,210],"rectangular":[95],"coarse-grain":[96],"floorplan.":[97],"Independent":[98],"compilation":[99,205],"made":[103],"possible":[104],"by":[105,136,207],"inserting":[106],"complementary":[107],"elastic":[108],"buffers":[109],"on":[110,213],"inter-tile":[111],"paths":[112,117],"ensure":[114],"these":[116],"are":[118],"not":[119],"bottleneck":[121],".":[127],"As":[128],"result,":[130],"an":[131],"formed":[135],"only":[137,196],"\u201cstitching\u201d":[138],"set":[140,187],"pre-compiled":[142,176],"tiles.We":[143],"show":[144],"compared":[146],"flat":[149],"flow,":[150],"our":[151,169],"results":[154],"in":[155,195,211],"higher":[156],"degrades":[162],"little":[163],"with":[164],"increasing":[165],"size.":[167],"Further,":[168],"generate":[172],"library":[174,189],"reused":[181],"-":[182],"it":[183],"stitch":[185],"new":[193],"35":[197],"minutes.":[198],"It":[199],"also":[200],"allows":[201],"divide-and-conquer":[203],"compiling":[208],"its":[209],"multiple":[214],"machines.":[215]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}