{"id":"https://openalex.org/W2154183349","doi":"https://doi.org/10.1109/fpl.2014.6927435","title":"A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs","display_name":"A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2154183349","doi":"https://doi.org/10.1109/fpl.2014.6927435","mag":"2154183349"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927435","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927435","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049970983","display_name":"Keitaro Takizawa","orcid":null},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Keitaro Takizawa","raw_affiliation_strings":["University of Aizu, Japan"],"affiliations":[{"raw_affiliation_string":"University of Aizu, Japan","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060673603","display_name":"Shunya Hosaka","orcid":null},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shunya Hosaka","raw_affiliation_strings":["University of Aizu, Japan"],"affiliations":[{"raw_affiliation_string":"University of Aizu, Japan","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101457695","display_name":"Hiroshi Saito","orcid":"https://orcid.org/0000-0002-5667-4085"},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroshi Saito","raw_affiliation_strings":["University of Aizu, Japan"],"affiliations":[{"raw_affiliation_string":"University of Aizu, Japan","institution_ids":["https://openalex.org/I141591182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049970983"],"corresponding_institution_ids":["https://openalex.org/I141591182"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.61644366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8131598830223083},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7918436527252197},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6314864158630371},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6105330586433411},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5867261290550232},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.5087838768959045},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5058131217956543},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.48980069160461426},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46380284428596497},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.432604044675827},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4257428050041199},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39040571451187134},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.13281452655792236},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10703793168067932},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07466161251068115}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8131598830223083},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7918436527252197},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6314864158630371},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6105330586433411},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5867261290550232},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.5087838768959045},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5058131217956543},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.48980069160461426},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46380284428596497},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.432604044675827},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4257428050041199},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39040571451187134},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.13281452655792236},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10703793168067932},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07466161251068115},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2014.6927435","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927435","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1514480347","https://openalex.org/W2013876999","https://openalex.org/W2014019899","https://openalex.org/W2033045135","https://openalex.org/W2036605181","https://openalex.org/W6630761995","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W2085028021","https://openalex.org/W3094139610","https://openalex.org/W2187164010","https://openalex.org/W1993985975","https://openalex.org/W4312516786","https://openalex.org/W2138474603","https://openalex.org/W2146990170","https://openalex.org/W937897205","https://openalex.org/W2380707529"],"abstract_inverted_index":{"In":[0,48],"this":[1],"paper,":[2],"we":[3,51],"propose":[4],"a":[5,24],"design":[6,28],"support":[7,29],"tool":[8,30,58],"set":[9,31,59],"for":[10,45],"asynchronous":[11],"circuits":[12,54],"with":[13,69],"bundled-data":[14,46],"implementation":[15],"to":[16,36],"implement":[17],"them":[18],"on":[19],"commercial":[20],"FPGAs":[21],"easily":[22],"considering":[23],"latency":[25],"constraint.":[26],"The":[27],"consists":[32],"of":[33],"six":[34],"tools":[35],"automate":[37],"constraint":[38],"generation,":[39],"timing":[40],"verification,":[41],"and":[42,60,66],"delay":[43],"adjustment":[44],"implementation.":[47],"the":[49,56,70],"experiments,":[50],"synthesize":[52],"two":[53],"using":[55],"proposed":[57],"compare":[61],"area,":[62],"performance,":[63],"power":[64],"consumption,":[65],"energy":[67],"consumption":[68],"synchronous":[71],"counterparts.":[72]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
