{"id":"https://openalex.org/W2066982505","doi":"https://doi.org/10.1109/fpl.2014.6927429","title":"Pattern-based FPGA logic block and clustering algorithm","display_name":"Pattern-based FPGA logic block and clustering algorithm","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2066982505","doi":"https://doi.org/10.1109/fpl.2014.6927429","mag":"2066982505"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/201909","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland"],"affiliations":[{"raw_affiliation_string":"Ecole Poly technique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"\u00c9cole Polyt\u00e9chnique F\u00e9d\u00e9rale de Lausanne (EPFL), Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.11179972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7421520352363586},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7089225053787231},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7054185271263123},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5970431566238403},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5383395552635193},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.534220278263092},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5294556021690369},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.5130430459976196},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5117337703704834},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5084613561630249},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5012216567993164},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.491986483335495},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48377248644828796},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4637627601623535},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4559415578842163},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2523133158683777},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1569734811782837},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15388014912605286}],"concepts":[{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7421520352363586},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7089225053787231},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7054185271263123},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5970431566238403},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5383395552635193},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.534220278263092},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5294556021690369},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.5130430459976196},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5117337703704834},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5084613561630249},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5012216567993164},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.491986483335495},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48377248644828796},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4637627601623535},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4559415578842163},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2523133158683777},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1569734811782837},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15388014912605286},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/fpl.2014.6927429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.955.4065","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.955.4065","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://infoscience.epfl.ch/record/201909/files/fpl14_final.pdf","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:201909","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/201909","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:infoscience.epfl.ch:228126","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/228126","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:201909","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/201909","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1530195145","https://openalex.org/W1790735265","https://openalex.org/W1842839060","https://openalex.org/W1966460368","https://openalex.org/W2029031086","https://openalex.org/W2038318386","https://openalex.org/W2055251702","https://openalex.org/W2095431940","https://openalex.org/W2109220922","https://openalex.org/W2111756578","https://openalex.org/W2113645429","https://openalex.org/W2138383740","https://openalex.org/W2138515016","https://openalex.org/W2138840350","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2155316178","https://openalex.org/W2238547494","https://openalex.org/W2248628119","https://openalex.org/W2288668669","https://openalex.org/W2401203270","https://openalex.org/W2540066750","https://openalex.org/W4243467301","https://openalex.org/W6680834870","https://openalex.org/W6728851518"],"related_works":["https://openalex.org/W2135636985","https://openalex.org/W2480852620","https://openalex.org/W3023652529","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2134262422","https://openalex.org/W2151927748","https://openalex.org/W4252906329","https://openalex.org/W2171679639","https://openalex.org/W2168296541"],"abstract_inverted_index":{"In":[0],"classical":[1],"FPGA,":[2],"LUTs":[3],"and":[4,10,56,67],"DFFs":[5],"are":[6,13],"pre-packed":[7],"into":[8,15],"BLEs":[9,12],"then":[11],"grouped":[14],"logic":[16,22,33,47],"blocks.":[17,34,48],"We":[18],"propose":[19],"a":[20,63,68,73],"novel":[21,54],"block":[23],"architecture":[24,55,80],"with":[25,72],"fast":[26],"combinational":[27],"paths":[28],"between":[29],"LUTs,":[30],"called":[31],"pattern-based":[32,46],"A":[35],"new":[36],"clustering":[37,59],"algorithm":[38,60],"is":[39],"developed":[40],"to":[41,62,78],"release":[42],"the":[43,53,57],"potential":[44],"of":[45],"Experimental":[49],"results":[50],"show":[51],"that":[52],"associated":[58],"lead":[61],"14%":[64],"performance":[65],"gain":[66],"8%":[69],"wirelength":[70],"reduction":[71],"3%":[74],"area":[75],"overhead":[76],"compared":[77],"conventional":[79],"in":[81],"large":[82],"control-instensive":[83],"benchmarks.":[84]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
