{"id":"https://openalex.org/W1980331539","doi":"https://doi.org/10.1109/fpl.2014.6927417","title":"Area implications of memory partitioning for high-level synthesis on FPGAs","display_name":"Area implications of memory partitioning for high-level synthesis on FPGAs","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W1980331539","doi":"https://doi.org/10.1109/fpl.2014.6927417","mag":"1980331539"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2014.6927417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025764181","display_name":"Luca Gallo","orcid":"https://orcid.org/0000-0002-2160-8467"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]},{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["GB","IT"],"is_corresponding":false,"raw_author_name":"Luca Gallo","raw_affiliation_strings":["Imperial College London, London, U.K","University of Naples Federico II, Napoli"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"University of Naples Federico II, Napoli","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088628660","display_name":"Alessandro Cilardo","orcid":"https://orcid.org/0000-0002-1685-8736"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Cilardo","raw_affiliation_strings":["University of Naples Federico II, Napoli"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Naples Federico II, Napoli","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081452934","display_name":"David B. Thomas","orcid":"https://orcid.org/0000-0002-9671-0917"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Thomas","raw_affiliation_strings":["Imperial College London, London, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085413241","display_name":"Samuel Bayliss","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Samuel Bayliss","raw_affiliation_strings":["Imperial College London, London, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Imperial College London, London, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7924090623855591},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5870639085769653},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5753188729286194},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.531959056854248},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.45427262783050537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44369035959243774},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4346499443054199},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4320247769355774},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.42981192469596863},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21229839324951172},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19462016224861145},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0708802342414856}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7924090623855591},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5870639085769653},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5753188729286194},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.531959056854248},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.45427262783050537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44369035959243774},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4346499443054199},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4320247769355774},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.42981192469596863},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21229839324951172},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19462016224861145},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0708802342414856}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2014.6927417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2014.6927417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320309590","display_name":"Universit\u00e0 degli Studi di Napoli Federico II","ror":"https://ror.org/05290cv24"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1966558833","https://openalex.org/W1977157984","https://openalex.org/W1988382391","https://openalex.org/W2013719680","https://openalex.org/W2028342110","https://openalex.org/W2059712825","https://openalex.org/W2098925700","https://openalex.org/W2116227385","https://openalex.org/W2143230897","https://openalex.org/W2165972424","https://openalex.org/W3151034118","https://openalex.org/W4211248800","https://openalex.org/W4235262323","https://openalex.org/W4300702549"],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160632767","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W1973862904","https://openalex.org/W2077105843","https://openalex.org/W181593118"],"abstract_inverted_index":{"FPGAs":[0],"normally":[1],"have":[2],"numerous":[3],"independent":[4],"memory":[5,17,23,35,43,74],"banks":[6],"that":[7,93],"can":[8],"be":[9],"accessed":[10],"simultaneously,":[11],"potentially":[12],"offering":[13],"a":[14,20,72,88],"very":[15],"large":[16],"bandwidth.":[18],"Adopting":[19],"suitable":[21],"application-based":[22],"partitioning":[24,45,63,75,96],"strategy":[25],"is":[26],"thus":[27],"vital":[28],"to":[29,39,102],"take":[30],"full":[31],"advantage":[32],"of":[33,51,71,80],"the":[34,41,48,52,56,62,68,78,94],"architecture.":[36],"In":[37],"addition":[38],"improving":[40],"potential":[42],"bandwidth,":[44],"also":[46],"affects":[47],"area":[49,69,99],"complexity":[50],"generated":[53],"system":[54],"because":[55],"required":[57],"steering":[58],"logic":[59],"depends":[60],"on":[61],"scheme.":[64],"This":[65],"work":[66],"describes":[67],"implications":[70],"lattice-based":[73],"technique":[76,97],"in":[77],"context":[79],"high-level":[81],"synthesis":[82],"for":[83],"FPGAs.":[84],"Experimental":[85],"results":[86],"with":[87],"commercial":[89],"HLS":[90],"tool":[91],"show":[92],"proposed":[95],"improves":[98],"efficiency":[100],"compared":[101],"alternative":[103],"approaches.":[104]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
