{"id":"https://openalex.org/W2033493263","doi":"https://doi.org/10.1109/fpl.2013.6645522","title":"Optimizing under abstraction: Using prefetching to improve FPGA performance","display_name":"Optimizing under abstraction: Using prefetching to improve FPGA performance","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2033493263","doi":"https://doi.org/10.1109/fpl.2013.6645522","mag":"2033493263"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2013.6645522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101767631","display_name":"Hsin-Jung Yang","orcid":"https://orcid.org/0000-0002-0990-7763"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hsin-Jung Yang","raw_affiliation_strings":["Computer Science and A.I. Laboratory, Massachusetts Institute of Technology, USA","Comput. Sci. & A.I. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and A.I. Laboratory, Massachusetts Institute of Technology, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Comput. Sci. & A.I. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027505039","display_name":"Kermin Fleming","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kermin Fleming","raw_affiliation_strings":["Computer Science and A.I. Laboratory, Massachusetts Institute of Technology, USA","Comput. Sci. & A.I. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and A.I. Laboratory, Massachusetts Institute of Technology, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Comput. Sci. & A.I. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109306000","display_name":"Michael Adler","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL","US"],"is_corresponding":false,"raw_author_name":"Michael Adler","raw_affiliation_strings":["VSSAD Group, Intel Corporation, Israel","VSSAD Group Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VSSAD Group, Intel Corporation, Israel","institution_ids":["https://openalex.org/I4210104622"]},{"raw_affiliation_string":"VSSAD Group Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Emer","raw_affiliation_strings":["VSSAD Group Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VSSAD Group Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8766031265258789},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.7686348557472229},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7377470135688782},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6822266578674316},{"id":"https://openalex.org/keywords/stride","display_name":"STRIDE","score":0.5490916967391968},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5265453457832336},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4530493915081024},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4191361367702484},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40806758403778076},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2649312913417816},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.17009225487709045}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8766031265258789},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.7686348557472229},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7377470135688782},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6822266578674316},{"id":"https://openalex.org/C18007350","wikidata":"https://www.wikidata.org/wiki/Q7394815","display_name":"STRIDE","level":2,"score":0.5490916967391968},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5265453457832336},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4530493915081024},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4191361367702484},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40806758403778076},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2649312913417816},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.17009225487709045},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2013.6645522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1967869476","https://openalex.org/W2010128395","https://openalex.org/W2016558956","https://openalex.org/W2022128349","https://openalex.org/W2060736133","https://openalex.org/W2095353352","https://openalex.org/W2103330947","https://openalex.org/W2108666047","https://openalex.org/W2112313615","https://openalex.org/W2125305952","https://openalex.org/W2127303041","https://openalex.org/W2135144597","https://openalex.org/W2135438094","https://openalex.org/W2143285027","https://openalex.org/W2147050042","https://openalex.org/W2159767828","https://openalex.org/W2162773908","https://openalex.org/W2165354374","https://openalex.org/W2537450429","https://openalex.org/W3005250903","https://openalex.org/W4232854706","https://openalex.org/W4247641071","https://openalex.org/W4248446132","https://openalex.org/W4255238016","https://openalex.org/W6681759790","https://openalex.org/W6814873179"],"related_works":["https://openalex.org/W1984744919","https://openalex.org/W2132930690","https://openalex.org/W2770599040","https://openalex.org/W1901380330","https://openalex.org/W4248324254","https://openalex.org/W3017219868","https://openalex.org/W2901324294","https://openalex.org/W3009812692","https://openalex.org/W2105980483","https://openalex.org/W2075164989"],"abstract_inverted_index":{"In":[0,43],"an":[1,38,58],"effort":[2],"to":[3,70,87],"speed":[4],"the":[5,26,55],"development":[6],"of":[7,28,53,57],"FPGA-based":[8],"accelerators,":[9],"recent":[10],"research":[11],"has":[12],"focused":[13],"on":[14,83],"providing":[15],"FPGA":[16],"developers":[17],"with":[18],"memory":[19,62],"and":[20,85],"communications":[21],"abstractions.":[22],"Because":[23],"abstraction":[24],"decouples":[25],"function":[27],"these":[29,34],"interfaces":[30,36],"from":[31],"their":[32],"implementation,":[33],"new":[35],"present":[37],"enormous":[39],"opportunity":[40],"for":[41],"optimization.":[42],"this":[44],"paper":[45],"we":[46],"examine":[47],"stride":[48],"prefetching":[49,75],"as":[50],"a":[51],"means":[52],"improving":[54],"performance":[56],"automatically":[59],"synthesized,":[60],"abstract":[61],"hierarchy.":[63],"We":[64],"demonstrate,":[65],"by":[66,81],"applying":[67],"our":[68],"technique":[69],"several":[71],"large":[72],"benchmarks,":[73],"that":[74],"can":[76],"improve":[77],"preexisting":[78],"application":[79],"runtime":[80],"15%":[82],"average,":[84],"up":[86],"40%,":[88],"without":[89],"requiring":[90],"program":[91],"modification.":[92]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}