{"id":"https://openalex.org/W2000054975","doi":"https://doi.org/10.1109/fpl.2013.6645518","title":"A packet classifier using LUT cascades based on EVMDDS (k)","display_name":"A packet classifier using LUT cascades based on EVMDDS (k)","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2000054975","doi":"https://doi.org/10.1109/fpl.2013.6645518","mag":"2000054975"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2013.6645518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645518","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070734898","display_name":"Hiroki Nakahara","orcid":"https://orcid.org/0000-0002-5701-7466"},"institutions":[{"id":"https://openalex.org/I107139324","display_name":"Kagoshima University","ror":"https://ror.org/03ss88z23","country_code":"JP","type":"education","lineage":["https://openalex.org/I107139324"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroki Nakahara","raw_affiliation_strings":["Kagoshima University, Japan","KAGOSHIMA UNIV, Kagoshima, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kagoshima University, Japan","institution_ids":["https://openalex.org/I107139324"]},{"raw_affiliation_string":"KAGOSHIMA UNIV, Kagoshima, Japan","institution_ids":["https://openalex.org/I107139324"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111659377","display_name":"Tsutomu Sasao","orcid":null},"institutions":[{"id":"https://openalex.org/I16656306","display_name":"Meiji University","ror":"https://ror.org/02rqvrp93","country_code":"JP","type":"education","lineage":["https://openalex.org/I16656306"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tsutomu Sasao","raw_affiliation_strings":["Meiji University, Japan","Meiji Univ., Kawasaki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Meiji University, Japan","institution_ids":["https://openalex.org/I16656306"]},{"raw_affiliation_string":"Meiji Univ., Kawasaki, Japan","institution_ids":["https://openalex.org/I16656306"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101052791","display_name":"Munehiro Matsuura","orcid":null},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Munehiro Matsuura","raw_affiliation_strings":["Kyushu Institute of Technology, Japan","Kyushu Institute of Technology, Iizuka, Japan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kyushu Institute of Technology, Japan","institution_ids":["https://openalex.org/I207014233"]},{"raw_affiliation_string":"Kyushu Institute of Technology, Iizuka, Japan#TAB#","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7173,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.64288585,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"4","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9775999784469604,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7575905323028564},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7349370121955872},{"id":"https://openalex.org/keywords/byte","display_name":"Byte","score":0.6729862093925476},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6626344323158264},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.6028178334236145},{"id":"https://openalex.org/keywords/classifier","display_name":"Classifier (UML)","score":0.5600188374519348},{"id":"https://openalex.org/keywords/cartesian-product","display_name":"Cartesian product","score":0.48058414459228516},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4558486044406891},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.42636731266975403},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.42020735144615173},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41312357783317566},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38886189460754395},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3711402118206024},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.30321717262268066},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21420255303382874},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19227826595306396},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14301472902297974},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.09774962067604065},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.08888402581214905},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08199849724769592}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7575905323028564},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7349370121955872},{"id":"https://openalex.org/C43364308","wikidata":"https://www.wikidata.org/wiki/Q8799","display_name":"Byte","level":2,"score":0.6729862093925476},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6626344323158264},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.6028178334236145},{"id":"https://openalex.org/C95623464","wikidata":"https://www.wikidata.org/wiki/Q1096149","display_name":"Classifier (UML)","level":2,"score":0.5600188374519348},{"id":"https://openalex.org/C65236422","wikidata":"https://www.wikidata.org/wiki/Q173740","display_name":"Cartesian product","level":2,"score":0.48058414459228516},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4558486044406891},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.42636731266975403},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.42020735144615173},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41312357783317566},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38886189460754395},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3711402118206024},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.30321717262268066},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21420255303382874},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19227826595306396},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14301472902297974},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.09774962067604065},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.08888402581214905},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08199849724769592},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2013.6645518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645518","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W32718306","https://openalex.org/W1971289987","https://openalex.org/W1975959118","https://openalex.org/W1992811742","https://openalex.org/W2026164946","https://openalex.org/W2036066800","https://openalex.org/W2080267935","https://openalex.org/W2087924620","https://openalex.org/W2095999202","https://openalex.org/W2103189753","https://openalex.org/W2105379047","https://openalex.org/W2109666621","https://openalex.org/W2115477036","https://openalex.org/W2119706632","https://openalex.org/W2138838211","https://openalex.org/W2139252662","https://openalex.org/W2139751271","https://openalex.org/W2149479807","https://openalex.org/W2150702922","https://openalex.org/W2154395888","https://openalex.org/W2159669151","https://openalex.org/W2342134141","https://openalex.org/W2762210817","https://openalex.org/W3139681473","https://openalex.org/W4250447890","https://openalex.org/W4378744510","https://openalex.org/W6601365235","https://openalex.org/W6648603970","https://openalex.org/W6674254405","https://openalex.org/W6676183366","https://openalex.org/W6745011789"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W1576787868","https://openalex.org/W2144044430","https://openalex.org/W4383744680","https://openalex.org/W1971632278","https://openalex.org/W1991576731","https://openalex.org/W2102930677","https://openalex.org/W4224232716"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,24,65],"packet":[4,25,79],"classifier":[5,26],"using":[6,57],"multiple":[7],"LUT":[8,55],"cascades":[9,56],"based":[10],"on":[11,64],"edge-valued":[12],"multi-valued":[13],"decision":[14],"diagrams":[15],"(EVMDDs":[16],"(k)).":[17],"First,":[18],"set":[20],"of":[21],"rules":[22],"for":[23,77,84],"is":[27,74,92],"partitioned":[28],"into":[29,35],"groups.":[30],"Second,":[31],"they":[32,43,51],"are":[33,44,52],"decomposed":[34],"field":[36],"functions":[37],"and":[38,49],"Cartesian":[39],"product":[40],"functions.":[41],"Third,":[42],"represented":[45],"by":[46],"EVMDDs":[47],"(k),":[48],"finally,":[50],"converted":[53],"to":[54],"adders.":[58],"We":[59],"implemented":[60],"the":[61,85,89],"proposed":[62,90],"circuit":[63],"Virtex":[66],"7":[67],"VC707":[68],"evaluation":[69],"board.":[70],"The":[71],"system":[72],"throughput":[73,87],"345.60":[75],"Gbps":[76],"minimum":[78],"size":[80],"(40":[81],"Bytes).":[82],"As":[83],"normalized":[86],"(efficiency),":[88],"one":[91],"7.14":[93],"times":[94],"better":[95],"than":[96],"existing":[97],"FPGA":[98],"implementations.":[99]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
