{"id":"https://openalex.org/W1978565299","doi":"https://doi.org/10.1109/fpl.2013.6645505","title":"In pursuit of instant gratification for FPGA design","display_name":"In pursuit of instant gratification for FPGA design","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1978565299","doi":"https://doi.org/10.1109/fpl.2013.6645505","mag":"1978565299"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2013.6645505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022398248","display_name":"Andrew Love","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Love","raw_affiliation_strings":["Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061668573","display_name":"Wenwei Zha","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wenwei Zha","raw_affiliation_strings":["Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111933984","display_name":"Peter Athanas","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Athanas","raw_affiliation_strings":["Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":4.4583,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.95421113,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.8249456882476807},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.810776948928833},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7163410782814026},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6291395425796509},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5896332859992981},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.5473315119743347},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.43424832820892334},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36848315596580505},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34081506729125977},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.26985761523246765},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.13028430938720703}],"concepts":[{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.8249456882476807},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.810776948928833},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7163410782814026},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6291395425796509},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5896332859992981},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.5473315119743347},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.43424832820892334},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36848315596580505},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34081506729125977},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.26985761523246765},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.13028430938720703},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2013.6645505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1587494897","https://openalex.org/W1980164533","https://openalex.org/W1988983317","https://openalex.org/W2059553661","https://openalex.org/W2067272463","https://openalex.org/W2084478983","https://openalex.org/W2101906611","https://openalex.org/W2103260577","https://openalex.org/W2115350349","https://openalex.org/W2117513278","https://openalex.org/W2119747185","https://openalex.org/W2126343776","https://openalex.org/W2127765551","https://openalex.org/W2135660453","https://openalex.org/W2139637699","https://openalex.org/W2145897936","https://openalex.org/W2151758817","https://openalex.org/W2155560344","https://openalex.org/W2158544590","https://openalex.org/W2540275465","https://openalex.org/W2592905981","https://openalex.org/W4238593108","https://openalex.org/W6674673547","https://openalex.org/W6677884726","https://openalex.org/W6679868426"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W2121309702","https://openalex.org/W1982685694","https://openalex.org/W49599899","https://openalex.org/W4311839959","https://openalex.org/W3217774925","https://openalex.org/W2040087757"],"abstract_inverted_index":{"This":[0,95],"paper":[1],"describes":[2],"an":[3],"alternative":[4],"FPGA":[5,19],"design":[6],"compilation":[7,63,75],"flow":[8,97],"to":[9,15],"reduce":[10],"the":[11,41,58],"back-end":[12,45],"time":[13,42,102],"required":[14],"implement":[16],"a":[17,22,38,85],"Xilinx":[18],"design.":[20],"Using":[21],"library":[23],"of":[24,32,40,43,61],"precompiled":[25],"modules":[26],"and":[27,51,106],"associated":[28],"meta-data,":[29],"bitstream-level":[30],"assembly":[31,56],"desired":[33],"designs":[34],"can":[35,76,90],"occur":[36],"in":[37,79,93],"fraction":[39],"traditional":[44],"tools.":[46],"Modules":[47],"are":[48,70],"bound,":[49],"placed,":[50],"routed":[52],"using":[53],"custom":[54],"bitstream":[55],"with":[57],"primary":[59],"objective":[60],"rapid":[62],"while":[64],"preserving":[65],"performance.":[66],"Since":[67],"vendor":[68],"tools":[69],"not":[71],"needed":[72],"for":[73,103],"assembly,":[74],"be":[77,91],"performed":[78],"embedded":[80],"and/or":[81],"untethered":[82],"environments.":[83],"As":[84],"result,":[86],"large":[87],"device":[88],"compilations":[89],"assembled":[92],"seconds.":[94],"turbo":[96],"(TFlow)":[98],"enables":[99],"software-like":[100],"turn-around":[101],"faster":[104],"prototyping":[105],"increased":[107],"productivity.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
