{"id":"https://openalex.org/W2005746619","doi":"https://doi.org/10.1109/fpl.2013.6645498","title":"Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation","display_name":"Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2005746619","doi":"https://doi.org/10.1109/fpl.2013.6645498","mag":"2005746619"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2013.6645498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052267211","display_name":"Anup Das","orcid":"https://orcid.org/0000-0002-5673-2636"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Anup Das","raw_affiliation_strings":["National University of Singapore, Singapore","National University of Singapore, Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"National University of Singapore, Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013017009","display_name":"Shyamsundar Venkataraman","orcid":null},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Shyamsundar Venkataraman","raw_affiliation_strings":["National University of Singapore, Singapore","National University of Singapore, Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"National University of Singapore, Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["National University of Singapore, Singapore","National University of Singapore, Singapore, Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"National University of Singapore, Singapore, Singapore","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5052267211"],"corresponding_institution_ids":["https://openalex.org/I165932596"],"apc_list":null,"apc_paid":null,"fwci":1.4187,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.83155755,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7968517541885376},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7717437148094177},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7702159285545349},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5945062041282654},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5054044723510742},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49185895919799805},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4510025382041931},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.4264594614505768},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36687368154525757},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.14449533820152283},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09782075881958008}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7968517541885376},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7717437148094177},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7702159285545349},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5945062041282654},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5054044723510742},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49185895919799805},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4510025382041931},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.4264594614505768},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36687368154525757},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.14449533820152283},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09782075881958008},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2013.6645498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2013.6645498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Conference on Field programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:scholarbank.nus.edu.sg:10635/83835","is_oa":false,"landing_page_url":"http://scholarbank.nus.edu.sg/handle/10635/83835","pdf_url":null,"source":{"id":"https://openalex.org/S7407052290","display_name":"National University of Singapore","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1527974875","https://openalex.org/W2013784404","https://openalex.org/W2014919515","https://openalex.org/W2039188166","https://openalex.org/W2096132155","https://openalex.org/W2100921984","https://openalex.org/W2114556285","https://openalex.org/W2119901643","https://openalex.org/W2135743241","https://openalex.org/W2148423020","https://openalex.org/W2150650385","https://openalex.org/W2154207336","https://openalex.org/W2158636214","https://openalex.org/W2166579337","https://openalex.org/W2171549192","https://openalex.org/W4237252402","https://openalex.org/W4240833370","https://openalex.org/W4248422778","https://openalex.org/W6682854392"],"related_works":["https://openalex.org/W2061783171","https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2540393334","https://openalex.org/W2131696304","https://openalex.org/W1983570530","https://openalex.org/W2390042878"],"abstract_inverted_index":{"Soft-errors":[0],"in":[1,41,143],"LUT":[2,59,65,68],"configuration":[3],"bits":[4],"of":[5,11,30,37,53,76,100,115],"FPGAs":[6],"can":[7,136],"alter":[8],"the":[9,35,94,116,128],"functionality":[10],"an":[12,103,132],"implemented":[13],"design,":[14],"rendering":[15],"it":[16],"useless,":[17],"unless":[18],"re-programmed.":[19],"This":[20],"paper":[21],"proposes":[22],"a":[23,31,73,140],"technique":[24,44],"to":[25,56,127],"improve":[26],"autonomous":[27],"fault-masking":[28,108,135],"capabilities":[29],"design":[32,118],"by":[33,102,121],"maximizing":[34],"number":[36],"zeros":[38],"or":[39],"ones":[40],"LUTs.":[42],"The":[43,113],"utilizes":[45],"spare":[46],"resources":[47],"(XOR":[48],"gates":[49],"and":[50,67,82],"carry":[51],"chain)":[52],"FPGA":[54,90],"devices":[55],"selectively":[57],"manipulate":[58],"contents":[60],"using":[61],"two":[62],"operations":[63],"-":[64],"restructuring":[66],"decomposition.":[69],"Experiments":[70],"conducted":[71],"with":[72,109,139],"wide":[74],"set":[75],"benchmarks":[77],"from":[78],"MCNC,":[79],"IWLS":[80],"2005":[81],"ITC99":[83],"benchmark":[84],"suite":[85],"on":[86,123],"Xilinx":[87],"Virtex":[88],"6":[89],"board":[91],"demonstrate":[92],"that":[93],"proposed":[95],"methodology":[96],"maximizes":[97],"logic":[98],"0/1":[99],"LUTs":[101],"average":[104,124],"20%":[105],"achieving":[106],"80%":[107],"no":[110],"area":[111],"overhead.":[112],"fault-rate":[114],"entire":[117],"is":[119],"reduced":[120],"60%":[122],"as":[125],"compared":[126],"existing":[129],"techniques.":[130],"Further,":[131],"additional":[133],"5%":[134],"be":[137],"achieved":[138],"7%":[141],"increase":[142],"slice":[144],"usage.":[145]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}