{"id":"https://openalex.org/W2075137913","doi":"https://doi.org/10.1109/fpl.2012.6339278","title":"Analytical placement for heterogeneous FPGAs","display_name":"Analytical placement for heterogeneous FPGAs","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2075137913","doi":"https://doi.org/10.1109/fpl.2012.6339278","mag":"2075137913"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2012.6339278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089383052","display_name":"Marcel Gort","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Marcel Gort","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Canada","Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason H. Anderson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Canada","Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Univ. of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089383052"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":4.2441,"has_fulltext":false,"cited_by_count":89,"citation_normalized_percentile":{"value":0.94535418,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"150"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7840145826339722},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7276344299316406},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7082056999206543},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6696743965148926},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6492552757263184},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6304218769073486},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5945340394973755},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5684319734573364},{"id":"https://openalex.org/keywords/placer-mining","display_name":"Placer mining","score":0.5576269626617432},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5421628952026367},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4498603940010071},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3207095265388489},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28262388706207275},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2754259705543518},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.22521868348121643},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.12982013821601868}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7840145826339722},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7276344299316406},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7082056999206543},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6696743965148926},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6492552757263184},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6304218769073486},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5945340394973755},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5684319734573364},{"id":"https://openalex.org/C43592290","wikidata":"https://www.wikidata.org/wiki/Q12148490","display_name":"Placer mining","level":2,"score":0.5576269626617432},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5421628952026367},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4498603940010071},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3207095265388489},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28262388706207275},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2754259705543518},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.22521868348121643},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.12982013821601868},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2012.6339278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.656.5230","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.656.5230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://janders.eecg.toronto.edu/pdfs/marcelfpl12.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1986026297","https://openalex.org/W2018055497","https://openalex.org/W2023788229","https://openalex.org/W2057807751","https://openalex.org/W2067446923","https://openalex.org/W2104079056","https://openalex.org/W2114820519","https://openalex.org/W2120129706","https://openalex.org/W2139637699","https://openalex.org/W2151758817","https://openalex.org/W2161531333","https://openalex.org/W2162969296","https://openalex.org/W2163961680","https://openalex.org/W6680692090"],"related_works":["https://openalex.org/W2366554144","https://openalex.org/W2003435315","https://openalex.org/W2024574431","https://openalex.org/W4239932082","https://openalex.org/W2083030004","https://openalex.org/W2140645577","https://openalex.org/W2132668926","https://openalex.org/W2028789485","https://openalex.org/W2134697552","https://openalex.org/W2477477398"],"abstract_inverted_index":{"We":[0,111],"present":[1],"HeAP,":[2],"an":[3,85,115],"analytical":[4,26],"placement":[5,129],"algorithm":[6],"for":[7],"heterogeneous":[8,32],"FPGAs":[9,30],"comprised":[10],"of":[11,46,77,96],"LUT-based":[12,47],"logic":[13],"blocks,":[14],"multiplier/DSP":[15],"blocks":[16,33,48],"and":[17,84,103,120],"block":[18],"RAMs.":[19],"Specifically,":[20],"we":[21],"adapt":[22],"a":[23,63,78,97,104,122],"state-of-the-art":[24],"ASIC-based":[25],"placer":[27,42,61,119],"to":[28,69,89],"target":[29],"with":[31,49,114,126],"located":[34],"at":[35,74,93],"discrete":[36],"locations":[37],"throughout":[38],"the":[39,75,94],"fabric.":[40],"Our":[41],"also":[43,112],"handles":[44],"macros":[45],"specific":[50],"layout":[51],"requirements,":[52],"such":[53],"as":[54],"carry":[55],"chains.":[56],"Results":[57],"show":[58],"that":[59],"our":[60],"delivers":[62],"4\u00d7":[64],"speedup,":[65],"on":[66],"average,":[67],"compared":[68,88],"Altera's":[70,90],"non-timing":[71],"driven":[72],"flow,":[73,92],"cost":[76,95],"5%":[79],"increase":[80,99],"in":[81,100,107],"postrouted":[82],"wirelength,":[83],"11\u00d7":[86],"speedup":[87],"timing-driven":[91],"4%":[98],"post-routed":[101],"wirelength":[102],"9%":[105],"reduction":[106],"maximum":[108],"operating":[109],"frequency.":[110],"compare":[113],"academic":[116],"simulated":[117],"annealing-based":[118],"demonstrate":[121],"7.4\u00d7":[123],"runtime":[124],"advantage":[125],"6%":[127],"better":[128],"quality.":[130]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":16},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
