{"id":"https://openalex.org/W1994202030","doi":"https://doi.org/10.1109/fpl.2012.6339269","title":"A two-stage variation-aware placement method for FPGAS exploiting variation maps classification","display_name":"A two-stage variation-aware placement method for FPGAS exploiting variation maps classification","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W1994202030","doi":"https://doi.org/10.1109/fpl.2012.6339269","mag":"1994202030"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2012.6339269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083017828","display_name":"Zhenyu Guan","orcid":"https://orcid.org/0000-0002-3959-338X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Zhenyu Guan","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056146508","display_name":"Sumanta Chaudhuri","orcid":"https://orcid.org/0000-0002-8337-079X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sumanta Chaudhuri","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Constantinides","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5083017828"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.491,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.66965826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"519","last_page":"522"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.8640179634094238},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.83781898021698},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.747060239315033},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.632605791091919},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.5366674661636353},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.5231496095657349},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.510562539100647},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.41519638895988464},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30785077810287476},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13790184259414673},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.07968080043792725},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07476478815078735},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.07120782136917114},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.06837025284767151}],"concepts":[{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.8640179634094238},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.83781898021698},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.747060239315033},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.632605791091919},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.5366674661636353},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.5231496095657349},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.510562539100647},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.41519638895988464},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30785077810287476},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13790184259414673},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.07968080043792725},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07476478815078735},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.07120782136917114},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.06837025284767151},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2012.6339269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04516503v1","is_oa":false,"landing_page_url":"https://telecom-paris.hal.science/hal-04516503","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL), Aug 2012, Oslo, Norway. pp.519-522, ⟨10.1109/FPL.2012.6339269⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5524266619","display_name":null,"funder_award_id":"EP/I020357/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2016712281","https://openalex.org/W2054411746","https://openalex.org/W2096227207","https://openalex.org/W2103156522","https://openalex.org/W2108165851","https://openalex.org/W2117648153","https://openalex.org/W2120116751","https://openalex.org/W2126460975","https://openalex.org/W2139970490","https://openalex.org/W2154446814","https://openalex.org/W2155142975","https://openalex.org/W3099514962","https://openalex.org/W3147179393","https://openalex.org/W4245052796","https://openalex.org/W4251154776","https://openalex.org/W4254506919","https://openalex.org/W6680648649"],"related_works":["https://openalex.org/W2386430105","https://openalex.org/W2137012493","https://openalex.org/W1995056098","https://openalex.org/W3183044703","https://openalex.org/W2126460975","https://openalex.org/W2959030164","https://openalex.org/W1564147575","https://openalex.org/W2054411746","https://openalex.org/W1977505713","https://openalex.org/W2007503867"],"abstract_inverted_index":{"Technology":[0],"scaling":[1],"causes":[2],"increasing":[3],"and":[4,100],"unavoidable":[5],"delay":[6],"variability":[7],"in":[8,81,93,123],"FPGAs.":[9,114],"This":[10],"paper":[11],"proposes":[12],"a":[13,24,31,38,94,135],"2-stage":[14],"variation-aware":[15,56],"placement":[16,27,57,74],"method":[17,90],"that":[18,82],"benefits":[19],"from":[20,106],"the":[21,65,73,76],"optimality":[22],"of":[23,33,41,54,68,97,119,137],"full-chipwise":[25,141],"(chip-by-chip)":[26],"but":[28],"only":[29,58],"requires":[30],"fraction":[32],"total":[34],"execution":[35,86,132],"time":[36,133],"for":[37,75],"large":[39],"number":[40,53],"FPGAs":[42,78],"with":[43,111,127],"different":[44],"variation":[45,49,103],"patterns.":[46],"By":[47],"classifying":[48],"maps":[50,104],"into":[51],"finite":[52],"classes,":[55],"need":[59],"to":[60,71,84,140],"be":[61],"executed":[62],"based":[63],"on":[64],"median":[66],"map":[67],"each":[69],"class":[70,83],"produce":[72],"other":[77],"(variation":[79],"maps)":[80],"save":[85],"time.":[87],"Our":[88],"proposed":[89],"is":[91,121],"implemented":[92],"modified":[95],"version":[96],"VPR":[98],"5.0":[99],"verified":[101],"using":[102],"measured":[105],"129":[107],"DE0":[108],"boards":[109],"equipped":[110],"Cyclone":[112],"III":[113],"The":[115],"mean":[116],"timing":[117],"gain":[118],"7.36%":[120],"observed":[122],"20":[124],"MCNC":[125],"benchmarks":[126],"16":[128],"clusters,":[129],"while":[130],"reducing":[131],"by":[134],"factor":[136],"8":[138],"compared":[139],"placement.":[142]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}