{"id":"https://openalex.org/W2020099160","doi":"https://doi.org/10.1109/fpl.2012.6339229","title":"Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs","display_name":"Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2020099160","doi":"https://doi.org/10.1109/fpl.2012.6339229","mag":"2020099160"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2012.6339229","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339229","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087051382","display_name":"Kazuhiko Terada","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuhiko Terada","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053591489","display_name":"Hiroyuki Uzawa","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroyuki Uzawa","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110504981","display_name":"Namiko Ikeda","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Namiko Ikeda","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035994507","display_name":"Satoshi Shigematsu","orcid":"https://orcid.org/0000-0001-6083-1664"},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoshi Shigematsu","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029014038","display_name":"Nobuyuki Tanaka","orcid":"https://orcid.org/0000-0002-6373-2220"},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nobuyuki Tanaka","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050057263","display_name":"Masami Urano","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masami Urano","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi City, Kanagawa, 243-0198, Japan","institution_ids":["https://openalex.org/I2251713219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I2251713219"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"33","issue":null,"first_page":"639","last_page":"642"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.90997314453125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7339432239532471},{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.693758487701416},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6250617504119873},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5689816474914551},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5566702485084534},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.538108229637146},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4802877604961395},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4293321669101715},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4261196255683899},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4141700267791748},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38086172938346863}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.90997314453125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7339432239532471},{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.693758487701416},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6250617504119873},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5689816474914551},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5566702485084534},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.538108229637146},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4802877604961395},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4293321669101715},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4261196255683899},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4141700267791748},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38086172938346863},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2012.6339229","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339229","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2026700311","https://openalex.org/W2131539973"],"related_works":["https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W2018882851","https://openalex.org/W4230312832","https://openalex.org/W1982273910","https://openalex.org/W1929041301","https://openalex.org/W2032882110","https://openalex.org/W2127843031","https://openalex.org/W2125423773"],"abstract_inverted_index":{"Verification":[0],"of":[1,5,16,32,36,57,71],"the":[2,14,29,33,37,55,58,64,69,77],"hardware/software":[3],"functions":[4],"a":[6],"10-Gbit/s-class":[7],"large-scale":[8],"network":[9],"systems-on-a-chip":[10],"(NW":[11],"SoC)":[12],"requires":[13],"use":[15],"multiple":[17],"field":[18],"programmable":[19],"gate":[20],"array":[21],"(FPGA)":[22],"devices.":[23,42],"We":[24,43],"propose":[25],"two":[26],"schemes":[27,66],"for":[28,50],"efficient":[30],"mapping":[31],"design":[34,48],"data":[35,49],"NW":[38,46],"SoC":[39,47],"into":[40],"FPGA":[41,51],"implemented":[44],"practical":[45],"devices,":[52],"and":[53,75],"evaluated":[54],"effectiveness":[56],"schemes.":[59],"The":[60],"results":[61],"show":[62],"that":[63],"proposed":[65],"can":[67],"reduce":[68],"number":[70],"wires":[72],"by":[73,82],"13%":[74],"improve":[76],"register":[78],"access":[79],"cycle":[80],"time":[81],"28%.":[83]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
