{"id":"https://openalex.org/W2087536201","doi":"https://doi.org/10.1109/fpl.2012.6339162","title":"High-level linear projection circuit design optimization framework for FPGAs under over-clocking","display_name":"High-level linear projection circuit design optimization framework for FPGAs under over-clocking","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2087536201","doi":"https://doi.org/10.1109/fpl.2012.6339162","mag":"2087536201"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2012.6339162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339162","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079441335","display_name":"Rui Policarpo Duarte","orcid":"https://orcid.org/0000-0002-7060-4745"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Rui Policarpo Duarte","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, UK","Department of Electrical and Electronic Engineering, Imperial College London, SW7 2AZ, U.K"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, SW7 2AZ, U.K","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041150785","display_name":"Christos-Savvas Bouganis","orcid":"https://orcid.org/0000-0002-4906-4510"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Christos-Savvas Bouganis","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, UK","Department of Electrical and Electronic Engineering, Imperial College London, SW7 2AZ, U.K"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, SW7 2AZ, U.K","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5079441335"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.6051,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.69826391,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"723","last_page":"726"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7353455424308777},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6633544564247131},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.5789561867713928},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.531448483467102},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5012307167053223},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.46091559529304504},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42212098836898804},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4179466962814331},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37054723501205444},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3669917583465576},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34368863701820374},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3060063123703003},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.222461998462677},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13399794697761536},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09215542674064636}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7353455424308777},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6633544564247131},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.5789561867713928},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.531448483467102},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5012307167053223},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.46091559529304504},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42212098836898804},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4179466962814331},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37054723501205444},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3669917583465576},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34368863701820374},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3060063123703003},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.222461998462677},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13399794697761536},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09215542674064636},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2012.6339162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339162","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2020999234","https://openalex.org/W2071128523","https://openalex.org/W2099946155","https://openalex.org/W2127227484","https://openalex.org/W2137294391","https://openalex.org/W2162656364"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2144453115","https://openalex.org/W1991670063","https://openalex.org/W4242565052","https://openalex.org/W2999907514","https://openalex.org/W4388667102","https://openalex.org/W2080035745","https://openalex.org/W4210379803","https://openalex.org/W2134486854"],"abstract_inverted_index":{"Frequently,":[0],"the":[1,34,49,67,84,94,99,123,128,133,139,174],"high-level":[2,102],"algorithm":[3],"parameter":[4],"selection":[5],"and":[6,82,149],"its":[7,64,151],"mapping":[8],"into":[9,101],"hardware":[10,36,171],"are":[11,28,106],"considered":[12],"to":[13,19,38,55,70,92,109,168],"be":[14,39,71,116],"independent":[15],"processes,":[16],"often":[17,32],"leading":[18],"suboptimal":[20],"solutions.":[21],"When":[22],"DSP":[23],"applications":[24],"with":[25],"real-time":[26],"constraints":[27],"targeted,":[29],"it":[30],"is":[31,54],"desirable":[33],"resulting":[35],"system":[37],"clocked":[40],"at":[41],"as":[42,45],"high":[43],"frequency":[44,76],"possible.":[46],"Even":[47],"though":[48],"trend":[50],"in":[51,170],"modern":[52],"devices":[53],"provide":[56],"a":[57,158],"fabric":[58,100],"that":[59],"can":[60,115],"support":[61],"higher":[62],"frequencies,":[63],"variability":[65,97],"makes":[66],"design":[68],"tools":[69],"pessimistic":[72],"about":[73],"maximum":[74],"clock":[75,153],"estimates.":[77],"The":[78],"proposed":[79,140],"framework":[80,141],"optimizes":[81],"mitigates":[83],"probabilistic":[85],"behaviour":[86],"of":[87,96,98,122,157],"digital":[88],"circuits,":[89],"by":[90,138,145,163],"trying":[91],"expose":[93],"impact":[95],"algorithmic":[103],"specifications.":[104],"FPGAs":[105],"well":[107],"positioned":[108],"tackle":[110],"this":[111],"problem":[112],"because":[113],"they":[114],"reconfigured,":[117],"allowing":[118],"an":[119],"off-line":[120],"characterization":[121],"specific":[124],"device":[125],"before":[126],"implementing":[127],"complete":[129],"optimized":[130],"circuit":[131],"on":[132],"same":[134,175],"device.":[135],"Circuits":[136],"generated":[137],"outperform":[142],"typical":[143],"implementations,":[144],"minimizing":[146],"area,":[147],"errors,":[148],"maximizing":[150],"operating":[152],"frequency.":[154],"An":[155],"example":[156],"linear":[159],"projection":[160],"circuit,":[161],"over-clocked":[162],"232%,":[164],"shows":[165],"savings":[166],"up":[167],"39%":[169],"resources":[172],"for":[173],"target":[176],"PSNR":[177],"over":[178],"traditional":[179],"implementation.":[180]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
