{"id":"https://openalex.org/W2078478492","doi":"https://doi.org/10.1109/fpl.2012.6339160","title":"Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit","display_name":"Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2078478492","doi":"https://doi.org/10.1109/fpl.2012.6339160","mag":"2078478492"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2012.6339160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035438680","display_name":"Travis Manderson","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Travis Manderson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada","Department of Electrical and Computer Engineering, Schulich School of Engineering, Universiy of Calgary, ICT 402, 2500 University Drive NW, Alberta, Canada T2N 1N4"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Schulich School of Engineering, Universiy of Calgary, ICT 402, 2500 University Drive NW, Alberta, Canada T2N 1N4","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005447330","display_name":"L.E. Turner","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Laurence Turner","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada","Department of Electrical and Computer Engineering, Schulich School of Engineering, Universiy of Calgary, ICT 402, 2500 University Drive NW, Alberta, Canada T2N 1N4"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Schulich School of Engineering, Universiy of Calgary, ICT 402, 2500 University Drive NW, Alberta, Canada T2N 1N4","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035438680"],"corresponding_institution_ids":["https://openalex.org/I168635309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15633839,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"36","issue":null,"first_page":"715","last_page":"718"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.8140513896942139},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7751259207725525},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7298851013183594},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6758030652999878},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.656054675579071},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5774534940719604},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.5702738165855408},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.5538908243179321},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5420849919319153},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.43073326349258423},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.4114646315574646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3966865539550781},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3823864758014679},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2879572808742523},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2136474847793579},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.08517521619796753},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07213744521141052}],"concepts":[{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.8140513896942139},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7751259207725525},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7298851013183594},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6758030652999878},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.656054675579071},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5774534940719604},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.5702738165855408},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.5538908243179321},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5420849919319153},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.43073326349258423},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.4114646315574646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3966865539550781},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3823864758014679},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2879572808742523},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2136474847793579},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.08517521619796753},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07213744521141052},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2012.6339160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2012.6339160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"22nd International Conference on Field Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2083326997","https://openalex.org/W2120110802","https://openalex.org/W2129513088","https://openalex.org/W2139195595","https://openalex.org/W2154656381","https://openalex.org/W2156142928","https://openalex.org/W2165837912","https://openalex.org/W3128942091","https://openalex.org/W6683161564"],"related_works":["https://openalex.org/W2593976670","https://openalex.org/W2158685723","https://openalex.org/W2546612563","https://openalex.org/W1976249856","https://openalex.org/W3096907109","https://openalex.org/W2184818077","https://openalex.org/W3205148284","https://openalex.org/W2153963611","https://openalex.org/W2993141888","https://openalex.org/W2182511681"],"abstract_inverted_index":{"A":[0],"runtime":[1,82],"reconfigurable":[2],"Digital":[3],"Signal":[4],"Processing":[5],"(DSP)":[6],"unit":[7,99,104],"using":[8,105,123],"one's":[9],"complement":[10],"data":[11],"and":[12,33,46,115,122],"a":[13,54,102,106,119],"Minimum":[14],"Signed":[15],"Digit":[16],"(MSD)":[17],"multiplier":[18,23,86,108],"is":[19,68,109],"described.":[20],"The":[21,96],"MSD":[22],"changes":[24],"the":[25,35,44,48,51,57,65,73,77,81,85],"partial":[26,38],"product":[27,39],"shift-and-add":[28],"operations":[29,32],"to":[30,63,90,101,111],"shift-and-add/subtract":[31],"reduces":[34],"number":[36],"of":[37,50,60,72,76,84],"terms":[40],"by":[41],"half,":[42],"decreasing":[43],"size":[45],"increasing":[47],"speed":[49],"multiplier.":[52],"Using":[53],"carry-save":[55],"architecture,":[56],"propagation":[58],"delay":[59],"an":[61,92],"adder":[62],"add":[64],"carry-out":[66],"bits":[67],"eliminated.":[69],"Taking":[70],"advantage":[71],"deterministic":[74],"nature":[75],"desired":[78],"DSP":[79,98,103],"algorithm,":[80],"reconfiguration":[83],"can":[87],"be":[88,112],"pipelined":[89],"eliminate":[91],"added":[93],"set-up":[94],"state.":[95],"described":[97],"compared":[100],"conventional":[107],"shown":[110],"20%":[113],"faster":[114],"30%":[116],"smaller":[117],"for":[118],"32-bit":[120],"coefficient":[121],"Xilinx":[124],"Field":[125],"Programmable":[126],"Gate":[127],"Arrays":[128],"(FPGAs)":[129],"with":[130],"6-input":[131],"Look-Up":[132],"Tables":[133],"(LUTs).":[134]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}