{"id":"https://openalex.org/W2014176254","doi":"https://doi.org/10.1109/fpl.2009.5272551","title":"Data parallel FPGA workloads: Software versus hardware","display_name":"Data parallel FPGA workloads: Software versus hardware","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2014176254","doi":"https://doi.org/10.1109/fpl.2009.5272551","mag":"2014176254"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009732949","display_name":"Peter Yiannacouras","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Peter Yiannacouras","raw_affiliation_strings":["Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110755517","display_name":"J. Gregory Steffan","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Gregory Steffan","raw_affiliation_strings":["Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jonathan Rose","raw_affiliation_strings":["Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009732949"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":2.1439,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.87420729,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"51","last_page":"58"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8114954829216003},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7011040449142456},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6009572744369507},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5858304500579834},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5459418296813965},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.542521059513092},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4801173210144043},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.44639480113983154},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4346993863582611},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3552432656288147},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33948814868927},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19413122534751892}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8114954829216003},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7011040449142456},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6009572744369507},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5858304500579834},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5459418296813965},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.542521059513092},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4801173210144043},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.44639480113983154},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4346993863582611},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3552432656288147},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33948814868927},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19413122534751892},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/fpl.2009.5272551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.156.2259","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.156.2259","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~yiannac/docs/fpl09.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.157.7355","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.7355","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~steffan/papers/yiannac_fpl09.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.158.6365","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.158.6365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~jayar/pubs/yiannacouras/yiannacourasfpl09.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1995348478","https://openalex.org/W2040073568","https://openalex.org/W2097959379","https://openalex.org/W2102081656","https://openalex.org/W2139836711","https://openalex.org/W2145947338","https://openalex.org/W2146449469","https://openalex.org/W2161761794","https://openalex.org/W2340283629","https://openalex.org/W6703925202"],"related_works":["https://openalex.org/W17155033","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W1590307681","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2281932057","https://openalex.org/W4230310076","https://openalex.org/W1966261340"],"abstract_inverted_index":{"Commercial":[0],"soft":[1,33,53,106,111,144],"processors":[2,34,55],"are":[3],"unable":[4],"to":[5,20,139,163,200,202],"effectively":[6],"exploit":[7,21],"the":[8,99,122,161,196],"data":[9,49,63,175],"parallelism":[10],"present":[11],"in":[12,44,73,153,170],"many":[13],"embedded":[14,95],"systems":[15],"workloads,":[16],"requiring":[17],"FPGA":[18,86,117],"designers":[19,199],"it":[22],"(laboriously)":[23],"with":[24,36,69,89],"manual":[25,70],"hardware":[26,71,134,206],"design.":[27],"Recent":[28],"research":[29],"has":[30],"demonstrated":[31],"that":[32,121],"augmented":[35],"support":[37],"for":[38,48,60,198],"vector":[39,54,112,145],"instructions":[40],"provide":[41,56],"significant":[42],"improvements":[43,183],"performance":[45,78,126,185],"and":[46,77,114,132,177,188],"scalability":[47],"parallel":[50,64],"workloads.":[51],"These":[52],"a":[57,104],"software":[58],"environment":[59],"quickly":[61],"encoding":[62],"computation,":[65],"but":[66],"their":[67],"competitiveness":[68],"design":[72],"terms":[74,154],"of":[75,155],"area":[76,156,190],"remains":[79],"unknown.":[80],"In":[81],"this":[82],"work,":[83],"using":[84,141],"an":[85],"platform":[87],"equipped":[88],"DDR":[90],"memory":[91],"executing":[92],"data-parallel":[93],"EEMBC":[94],"benchmarks,":[96],"we":[97,168],"measure":[98],"area/performance":[100],"gaps":[101],"between":[102,128],"(i)":[103],"scalar":[105,129],"processor,":[107,113,146],"(ii)":[108],"our":[109,142],"improved":[110,143,150],"(iii)":[115],"custom":[116,133,171,205],"hardware.":[118],"We":[119,159],"demonstrate":[120],"432times":[123],"wall":[124],"clock":[125],"gap":[127],"executed":[130],"C":[131],"can":[135],"be":[136],"reduced":[137],"significantly":[138,194],"17times":[140],"while":[147],"silicon-efficiency":[148],"is":[149],"by":[151,186,191],"3times":[152,187],"delay":[157],"product.":[158],"modified":[160],"architecture":[162],"mitigate":[164],"three":[165],"key":[166],"advantages":[167],"observed":[169],"hardware:":[172],"loop":[173],"overhead,":[174],"delivery,":[176],"exact":[178],"resource":[179],"usage.":[180],"Combined":[181],"these":[182],"increase":[184],"reduce":[189],"almost":[192],"half,":[193],"reducing":[195],"need":[197],"resort":[201],"more":[203],"challenging":[204],"implementations.":[207]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}