{"id":"https://openalex.org/W2147753626","doi":"https://doi.org/10.1109/fpl.2009.5272548","title":"Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors","display_name":"Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2147753626","doi":"https://doi.org/10.1109/fpl.2009.5272548","mag":"2147753626"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015534628","display_name":"Nachiket Kapre","orcid":"https://orcid.org/0000-0002-2187-0406"},"institutions":[{"id":"https://openalex.org/I122411786","display_name":"California Institute of Technology","ror":"https://ror.org/05dxps055","country_code":"US","type":"education","lineage":["https://openalex.org/I122411786"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nachiket Kapre","raw_affiliation_strings":["Computer Science, California Institute of Technology, Pasadena, CA, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science, California Institute of Technology, Pasadena, CA, USA","institution_ids":["https://openalex.org/I122411786"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087585086","display_name":"Andr\u00e9 DeHon","orcid":"https://orcid.org/0000-0001-9177-7699"},"institutions":[{"id":"https://openalex.org/I79576946","display_name":"University of Pennsylvania","ror":"https://ror.org/00b30xv10","country_code":"US","type":"education","lineage":["https://openalex.org/I79576946"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andre DeHon","raw_affiliation_strings":["Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5015534628"],"corresponding_institution_ids":["https://openalex.org/I122411786"],"apc_list":null,"apc_paid":null,"fwci":3.7518,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":{"value":0.93781354,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8400470018386841},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7882211208343506},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6991697549819946},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.6088966131210327},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.543919563293457},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.5345598459243774},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.5276145935058594},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.5121957659721375},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.455194354057312},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.45482614636421204},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.2788267731666565},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2507149577140808},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10022759437561035},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08523780107498169}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8400470018386841},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7882211208343506},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6991697549819946},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.6088966131210327},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.543919563293457},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.5345598459243774},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.5276145935058594},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.5121957659721375},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.455194354057312},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.45482614636421204},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.2788267731666565},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2507149577140808},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10022759437561035},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08523780107498169},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/fpl.2009.5272548","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:authors.library.caltech.edu:18923","is_oa":false,"landing_page_url":"https://resolver.caltech.edu/CaltechAUTHORS:20100707-100125364","pdf_url":null,"source":{"id":"https://openalex.org/S4306402161","display_name":"CaltechAUTHORS (California Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122411786","host_organization_name":"California Institute of Technology","host_organization_lineage":["https://openalex.org/I122411786"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Book Section"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.233.2091","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.233.2091","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ic.ese.upenn.edu/pdf/spice_fpl2009.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.473.3328","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.473.3328","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://authors.library.caltech.edu/18923/1/Kapre2009p10508Fpl_2009_International_Conference_On_Field_Programmable_Logic_And_Applications.pdf","raw_type":"text"},{"id":"pmh:oai:dr.ntu.edu.sg:10356/81245","is_oa":false,"landing_page_url":"http://hdl.handle.net/10220/39197","pdf_url":null,"source":{"id":"https://openalex.org/S4306402609","display_name":"DR-NTU (Nanyang Technological University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172675005","host_organization_name":"Nanyang Technological University","host_organization_lineage":["https://openalex.org/I172675005"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W83535271","https://openalex.org/W1503406254","https://openalex.org/W2007480409","https://openalex.org/W2020732682","https://openalex.org/W2097814282","https://openalex.org/W2116586590","https://openalex.org/W2131947274","https://openalex.org/W2134963129","https://openalex.org/W2135653967","https://openalex.org/W2155946985","https://openalex.org/W2162585354","https://openalex.org/W2166214095","https://openalex.org/W2167078995","https://openalex.org/W2170116489","https://openalex.org/W3136479147","https://openalex.org/W3147150317","https://openalex.org/W3152338798","https://openalex.org/W6630221792","https://openalex.org/W6652027108","https://openalex.org/W6684855455"],"related_works":["https://openalex.org/W1897551170","https://openalex.org/W1507301366","https://openalex.org/W4385464314","https://openalex.org/W2048140838","https://openalex.org/W2170588811","https://openalex.org/W2265064666","https://openalex.org/W2095605415","https://openalex.org/W1953299766","https://openalex.org/W2118898240","https://openalex.org/W3211416786"],"abstract_inverted_index":{"Automated":[0],"code":[1,37,89],"generation":[2],"and":[3,14,134],"performance":[4],"tuning":[5],"techniques":[6],"for":[7,25,38,46,59,74,77,80,85,90,114,123,130,136,150],"concurrent":[8],"architectures":[9],"such":[10],"as":[11],"GPUs,":[12],"Cell":[13],"FPGAs":[15],"can":[16],"provide":[17],"integer":[18],"factor":[19],"speedups":[20,119],"over":[21,142],"multi-core":[22],"processor":[23],"organizations":[24],"data-parallel,":[26],"floating-point":[27],"computation":[28],"in":[29,48,63],"SPICE":[30,49],"model-evaluation.":[31],"Our":[32,66],"Verilog":[33],"AMS":[34],"compiler":[35,67],"produces":[36],"parallel":[39],"evaluation":[40],"of":[41,120,153],"non-linear":[42],"circuit":[43],"models":[44],"suitable":[45],"use":[47],"simulations":[50],"where":[51],"the":[52,61,64,110],"same":[53],"model":[54],"is":[55],"evaluated":[56],"several":[57],"times":[58],"all":[60],"devices":[62],"circuit.":[65],"uses":[68],"architecture":[69],"specific":[70],"parallelization":[71],"strategies":[72],"(OpenMP":[73],"multi-core,":[75],"PThreads":[76],"Cell,":[78,133],"CUDA":[79],"GPU,":[81],"statically":[82],"scheduled":[83],"VLIW":[84],"FPGA)":[86],"when":[87],"producing":[88],"these":[91],"different":[92,97],"architectures.":[93],"We":[94,117],"automatically":[95],"explore":[96],"implementation":[98,149],"configurations":[99],"(e.g.":[100],"unroll":[101],"factor,":[102],"vector":[103],"length)":[104],"using":[105],"our":[106],"performance-tuner":[107],"to":[108],"identify":[109],"best":[111],"possible":[112],"configuration":[113],"each":[115],"architecture.":[116],"demonstrate":[118],"3-":[121],"182times":[122],"a":[124,143,151],"Xilinx":[125],"Virtex5":[126],"LX":[127],"330T,":[128],"1.3-33times":[129],"an":[131,137],"IBM":[132],"3-131times":[135],"NVIDIA":[138],"9600":[139],"GT":[140],"GPU":[141],"3":[144],"GHz":[145],"Intel":[146],"Xeon":[147],"5160":[148],"variety":[152],"single-precision":[154],"device":[155],"models.":[156]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":7}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
