{"id":"https://openalex.org/W2059553661","doi":"https://doi.org/10.1109/fpl.2009.5272520","title":"Replace: An incremental placement algorithm for field programmable gate arrays","display_name":"Replace: An incremental placement algorithm for field programmable gate arrays","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2059553661","doi":"https://doi.org/10.1109/fpl.2009.5272520","mag":"2059553661"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272520","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272520","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032248008","display_name":"David Leong","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"David Leong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071113717","display_name":"Guy Lemieux","orcid":"https://orcid.org/0000-0002-7924-8695"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Guy G. F. Lemieux","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept of Electrical & Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5032248008"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.2183,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.80583132,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"154","last_page":"161"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7245085835456848},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.6890684366226196},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6345570087432861},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.6047666668891907},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5555331707000732},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5516100525856018},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4854762852191925},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.44119682908058167},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42875421047210693},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4274072051048279},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3305724859237671},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1905929148197174},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.15895572304725647},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07823684811592102}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7245085835456848},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.6890684366226196},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6345570087432861},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.6047666668891907},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5555331707000732},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5516100525856018},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4854762852191925},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.44119682908058167},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42875421047210693},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4274072051048279},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3305724859237671},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1905929148197174},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.15895572304725647},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07823684811592102},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2009.5272520","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272520","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.380.2808","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.380.2808","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~lemieux/publications/leong-fpl2009.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.4399999976158142,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1524185793","https://openalex.org/W1771324583","https://openalex.org/W1841603439","https://openalex.org/W1960552015","https://openalex.org/W1963908543","https://openalex.org/W2029541370","https://openalex.org/W2044115663","https://openalex.org/W2059553661","https://openalex.org/W2076489945","https://openalex.org/W2096185144","https://openalex.org/W2099108222","https://openalex.org/W2100735755","https://openalex.org/W2111756578","https://openalex.org/W2112904016","https://openalex.org/W2137381762","https://openalex.org/W2170702155","https://openalex.org/W3140066792","https://openalex.org/W3141147179"],"related_works":["https://openalex.org/W2180598069","https://openalex.org/W4256007160","https://openalex.org/W2094042791","https://openalex.org/W3153286430","https://openalex.org/W4205135025","https://openalex.org/W3015761757","https://openalex.org/W96081925","https://openalex.org/W2102616729","https://openalex.org/W1535529518","https://openalex.org/W2117901445"],"abstract_inverted_index":{"Recompiling":[0],"a":[1,6,11,55,58,115,172],"large":[2,43],"circuit":[3],"after":[4],"making":[5],"few":[7],"logic":[8],"changes":[9,30,41],"is":[10,23,36,49,61,77,112,136],"time-consuming":[12],"process.":[13,176],"We":[14],"present":[15],"an":[16,46],"incremental":[17,131,157],"placement":[18,132,158,169],"algorithm":[19,76,159],"for":[20,29],"FPGAs":[21],"that":[22],"focused":[24],"on":[25,92,106],"extremely":[26],"fast":[27,134],"runtime":[28],"which":[31,96],"can":[32],"be":[33],"localized.":[34],"It":[35],"capable":[37],"of":[38,45,103,125,162],"handling":[39],"multiple":[40],"across":[42],"regions":[44],"FPGA.":[47],"This":[48],"especially":[50],"useful":[51],"when":[52],"used":[53],"with":[54,146],"floorplan":[56],"where":[57,70],"modified":[59],"subcircuit":[60],"instantiated":[62],"several":[63,71],"times":[64,138],"in":[65,155],"the":[66,101,120,130,156],"design":[67],"hierarchy":[68],"or":[69],"subcircuits":[72],"are":[73,90,128],"modified.":[74],"The":[75,151],"simpler":[78],"and":[79,87,171],"faster":[80,139],"than":[81,140],"past":[82],"approaches":[83],"because":[84],"its":[85],"insertion":[86],"legalization":[88],"steps":[89,95],"based":[91],"CPU-efficient":[93,165],"shifting":[94],"do":[97],"not":[98],"continuously":[99],"evaluate":[100],"impact":[102],"each":[104],"move":[105],"costs.":[107],"Instead,":[108],"any":[109],"lost":[110],"quality":[111,149],"recovered":[113],"by":[114],"fast,":[116],"low-temperature":[117],"anneal":[118],"at":[119],"end.":[121],"When":[122],"35,000":[123],"out":[124],"50,000":[126],"LUTs":[127],"modified,":[129],"(including":[133],"anneal)":[135],"7":[137],"VPR's":[141],"\"fast":[142],"placement\"":[143],"from":[144],"scratch":[145],"only":[147],"2%":[148],"degradation.":[150],"key":[152],"concepts":[153],"utilized":[154],"include":[160],"uses":[161],"floor-planning":[163],"constraints,":[164],"CLB":[166],"shifting,":[167],"super":[168],"grid":[170],"tuned":[173],"annealing":[174],"refinement":[175]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
