{"id":"https://openalex.org/W2091636254","doi":"https://doi.org/10.1109/fpl.2009.5272373","title":"Using C-to-gates to program streaming image processing kernels efficiently on FPGAs","display_name":"Using C-to-gates to program streaming image processing kernels efficiently on FPGAs","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2091636254","doi":"https://doi.org/10.1109/fpl.2009.5272373","mag":"2091636254"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035560671","display_name":"Kristof Denolf","orcid":"https://orcid.org/0000-0001-6668-4562"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Kristof Denolf","raw_affiliation_strings":["IMEC, Leuven, Belgium","IMEC, Kapeldreef 75, 3001 Leuven Belgium,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"IMEC, Kapeldreef 75, 3001 Leuven Belgium,","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014827775","display_name":"Stephen Neuendorffer","orcid":"https://orcid.org/0000-0003-2956-8428"},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]},{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"Stephen Neuendorffer","raw_affiliation_strings":["Xilinx Research Laboratories, San Jose, CA, USA","LANNION/IRISA/CAIRN, 6 rue de Kerampont, 22300 France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Research Laboratories, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"LANNION/IRISA/CAIRN, 6 rue de Kerampont, 22300 France","institution_ids":["https://openalex.org/I2802519937"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011464762","display_name":"Kees Vissers","orcid":"https://orcid.org/0000-0002-6249-315X"},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]},{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"Kees Vissers","raw_affiliation_strings":["Xilinx Research Laboratories, San Jose, CA, USA","LANNION/IRISA/CAIRN, 6 rue de Kerampont, 22300 France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Research Laboratories, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"LANNION/IRISA/CAIRN, 6 rue de Kerampont, 22300 France","institution_ids":["https://openalex.org/I2802519937"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5259,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.83818573,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"626","last_page":"630"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8732413053512573},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7999420166015625},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6325900554656982},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6266385912895203},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5451703071594238},{"id":"https://openalex.org/keywords/range","display_name":"Range (aeronautics)","score":0.4710540473461151},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46837860345840454},{"id":"https://openalex.org/keywords/resource-consumption","display_name":"Resource consumption","score":0.4467933475971222},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.44403311610221863},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.4411439299583435},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.42719346284866333},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38727205991744995},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34627270698547363},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.32058611512184143},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.18514704704284668},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08457043766975403}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8732413053512573},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7999420166015625},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6325900554656982},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6266385912895203},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5451703071594238},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.4710540473461151},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46837860345840454},{"id":"https://openalex.org/C2777480716","wikidata":"https://www.wikidata.org/wiki/Q23582796","display_name":"Resource consumption","level":2,"score":0.4467933475971222},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.44403311610221863},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.4411439299583435},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.42719346284866333},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38727205991744995},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34627270698547363},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.32058611512184143},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.18514704704284668},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08457043766975403},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2009.5272373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1492631919","https://openalex.org/W1548598239","https://openalex.org/W1551441969","https://openalex.org/W2018540799","https://openalex.org/W2106111212","https://openalex.org/W2145308009","https://openalex.org/W2155325307"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2091330445","https://openalex.org/W2800543810","https://openalex.org/W2122674270","https://openalex.org/W4365793791"],"abstract_inverted_index":{"Effectively":[0],"exploiting":[1],"the":[2,19,81,85,88,93],"variety":[3],"of":[4,22,46,80],"computational":[5],"and":[6,63,76,92],"storage":[7],"resources":[8],"available":[9],"in":[10,28,58],"common":[11],"FPGA":[12,89],"architectures":[13],"for":[14],"complex":[15],"applications,":[16],"such":[17],"as":[18],"real-time":[20],"implementation":[21],"vision":[23,71],"algorithms,":[24],"is":[25,95],"often":[26],"difficult":[27],"standard":[29],"HDL":[30],"design":[31,34,39,61,86],"methodologies.":[32],"Higher-level":[33],"tools":[35],"can":[36],"enable":[37],"a":[38,44,59],"to":[40],"more":[41],"quickly":[42],"explore":[43],"range":[45],"different":[47],"architectures.":[48],"In":[49],"this":[50],"paper":[51],"we":[52],"apply":[53],"algorithmic":[54],"C-to-FPGA":[55],"synthesis":[56],"technology":[57],"structured":[60],"approach":[62,83],"demonstrate":[64],"its":[65],"added":[66],"value":[67],"on":[68,84],"two":[69],"relevant":[70],"processing":[72],"kernels:":[73],"optical":[74],"flow":[75],"debayering.":[77],"The":[78],"impact":[79],"proposed":[82],"time,":[87],"resource":[90],"consumption":[91],"throughput":[94],"measured.":[96]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
