{"id":"https://openalex.org/W1985032679","doi":"https://doi.org/10.1109/fpl.2009.5272349","title":"Compact FPGA implementation of Camellia","display_name":"Compact FPGA implementation of Camellia","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W1985032679","doi":"https://doi.org/10.1109/fpl.2009.5272349","mag":"1985032679"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272349","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272349","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055356305","display_name":"Panasayya Yalla","orcid":null},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Panasayya Yalla","raw_affiliation_strings":["Volgenau School of IT&E, George Mason University, Fairfax, VA, USA"],"affiliations":[{"raw_affiliation_string":"Volgenau School of IT&E, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039598410","display_name":"Jens-Peter Kaps","orcid":"https://orcid.org/0000-0002-7036-6433"},"institutions":[{"id":"https://openalex.org/I162714631","display_name":"George Mason University","ror":"https://ror.org/02jqj7156","country_code":"US","type":"education","lineage":["https://openalex.org/I162714631"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jens-Peter Kaps","raw_affiliation_strings":["Volgenau School of IT&E, George Mason University, Fairfax, VA, USA"],"affiliations":[{"raw_affiliation_string":"Volgenau School of IT&E, George Mason University, Fairfax, VA, USA","institution_ids":["https://openalex.org/I162714631"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5055356305"],"corresponding_institution_ids":["https://openalex.org/I162714631"],"apc_list":null,"apc_paid":null,"fwci":1.3549,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.84083484,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"658","last_page":"661"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8701419234275818},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7413038015365601},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6161327362060547},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5117866396903992},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5067098736763},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4646534323692322},{"id":"https://openalex.org/keywords/spartan","display_name":"Spartan","score":0.4205944836139679},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4159996509552002},{"id":"https://openalex.org/keywords/camellia","display_name":"Camellia","score":0.4118233323097229},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3319321870803833},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16666069626808167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13418704271316528},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.10303482413291931}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8701419234275818},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7413038015365601},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6161327362060547},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5117866396903992},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5067098736763},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4646534323692322},{"id":"https://openalex.org/C10689553","wikidata":"https://www.wikidata.org/wiki/Q405953","display_name":"Spartan","level":3,"score":0.4205944836139679},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4159996509552002},{"id":"https://openalex.org/C2780790598","wikidata":"https://www.wikidata.org/wiki/Q1028476","display_name":"Camellia","level":2,"score":0.4118233323097229},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3319321870803833},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16666069626808167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13418704271316528},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.10303482413291931},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2009.5272349","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272349","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.229.4157","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.229.4157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cryptography.gmu.edu/%7Ejkaps/download.php?docid=1209","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1487782177","https://openalex.org/W1489027369","https://openalex.org/W1568970091","https://openalex.org/W1588153376","https://openalex.org/W1836039892","https://openalex.org/W1868228027","https://openalex.org/W2122617332","https://openalex.org/W4285719527","https://openalex.org/W6629324062","https://openalex.org/W6638473360"],"related_works":["https://openalex.org/W3110137422","https://openalex.org/W3215016102","https://openalex.org/W2047513257","https://openalex.org/W2182587364","https://openalex.org/W1977065901","https://openalex.org/W2804202236","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"We":[0],"present":[1],"the":[2,57],"smallest":[3,58],"FPGA":[4],"implementation":[5,45],"of":[6,53],"Camellia":[7],"for":[8,18,32,39],"128-bit":[9],"key":[10],"length":[11],"to":[12],"date.":[13],"This":[14],"architecture":[15],"was":[16],"designed":[17],"low":[19,22],"area":[20],"and":[21,34],"power":[23],"applications.":[24],"Through":[25],"specific":[26],"optimizations":[27],"such":[28],"as":[29],"shift":[30],"registers":[31],"storing":[33,40],"scheduling":[35],"key,":[36],"distributed":[37],"RAM":[38],"data,":[41],"we":[42],"achieved":[43],"compact":[44],"using":[46],"only":[47],"318":[48],"slices":[49],"at":[50],"a":[51],"throughput":[52],"18.41":[54],"Mbps":[55],"on":[56],"Xilinx":[59],"Spartan-3":[60],"XC3S50-5":[61],"device.":[62]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
