{"id":"https://openalex.org/W2014112279","doi":"https://doi.org/10.1109/fpl.2009.5272298","title":"Area estimation and optimisation of FPGA routing fabrics","display_name":"Area estimation and optimisation of FPGA routing fabrics","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2014112279","doi":"https://doi.org/10.1109/fpl.2009.5272298","mag":"2014112279"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272298","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045144421","display_name":"Alastair Smith","orcid":"https://orcid.org/0000-0002-5291-1442"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Alastair M. Smith","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Department of Electrical and Electronic Engineering, Imperial College, London, Uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, Uk","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Department of Electrical and Electronic Engineering, Imperial College, London, Uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, Uk","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Department of Electrical and Electronic Engineering, Imperial College, London, Uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College, London, Uk","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045144421"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":1.2183,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.80107434,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"12","issue":null,"first_page":"256","last_page":"261"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.773247480392456},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7638732194900513},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7526421546936035},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5343479514122009},{"id":"https://openalex.org/keywords/geometric-programming","display_name":"Geometric programming","score":0.41125449538230896},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36949703097343445},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3661106824874878},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34096890687942505},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16252610087394714},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.08159983158111572}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.773247480392456},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7638732194900513},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7526421546936035},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5343479514122009},{"id":"https://openalex.org/C20729856","wikidata":"https://www.wikidata.org/wiki/Q2078279","display_name":"Geometric programming","level":2,"score":0.41125449538230896},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36949703097343445},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3661106824874878},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34096890687942505},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16252610087394714},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.08159983158111572}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2009.5272298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272298","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.386.53","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.386.53","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cas.ee.ic.ac.uk/people/gac1/pubs/AlFPL09.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[{"id":"https://openalex.org/G6672801631","display_name":null,"funder_award_id":"EP/E00024X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1684459694","https://openalex.org/W1989477191","https://openalex.org/W2035847677","https://openalex.org/W2113645429","https://openalex.org/W2121406505","https://openalex.org/W2131696304","https://openalex.org/W2145101431","https://openalex.org/W2151872233","https://openalex.org/W2296319761","https://openalex.org/W4250589301"],"related_works":["https://openalex.org/W2207963064","https://openalex.org/W4206794813","https://openalex.org/W2944709645","https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2184011203"],"abstract_inverted_index":{"This":[0,61],"paper":[1,46],"presents":[2],"a":[3,55,68],"methodology":[4],"for":[5,21],"estimating":[6],"and":[7,15,88,105],"optimising":[8],"FPGA":[9,58,82],"routing":[10,59,100],"fabrics":[11],"using":[12,120],"high-level":[13],"modelling":[14],"convex":[16],"optimisation":[17,71],"techniques.":[18],"Experimental":[19],"methods":[20],"exploring":[22],"design":[23],"spaces":[24],"suffer":[25],"from":[26],"expensive":[27],"computation":[28],"time,":[29],"which":[30],"is":[31,63],"exacerbated":[32],"by":[33],"increased":[34],"dimensionality":[35],"due":[36],"to":[37,53,78,112],"the":[38,86],"larger":[39],"number":[40],"of":[41,57,70,90,116,119,123],"architectural":[42,83],"parameters.":[43],"In":[44],"this":[45],"we":[47],"build":[48],"on":[49],"previously":[50],"published":[51],"work":[52],"describe":[54],"model":[56,62],"area.":[60],"used":[64],"in":[65,76,93],"conjunction":[66],"with":[67],"form":[69],"known":[72],"as":[73,103],"geometric":[74],"programming,":[75],"order":[77],"analytically":[79],"derive":[80],"optimised":[81],"parameters,":[84],"demonstrating":[85],"power":[87],"accuracy":[89],"model-based":[91],"approaches":[92],"configurable":[94],"architecture":[95],"design.":[96],"We":[97],"show":[98],"that":[99],"parameters":[101],"such":[102],"connection":[104],"switch":[106],"box":[107],"flexibilities":[108],"can":[109],"be":[110],"architected":[111],"save":[113],"around":[114],"6%":[115],"area":[117],"instead":[118],"traditional":[121],"ldquorules":[122],"thumbrdquo.":[124]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}