{"id":"https://openalex.org/W1983111999","doi":"https://doi.org/10.1109/fpl.2009.5272286","title":"Enhancements to FPGA design methodology using streaming","display_name":"Enhancements to FPGA design methodology using streaming","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W1983111999","doi":"https://doi.org/10.1109/fpl.2009.5272286","mag":"1983111999"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272286","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272286","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021489497","display_name":"Franjo Plavec","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Franjo Plavec","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035010641","display_name":"Z.G. Vranesic","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Zvonko Vranesic","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102840804","display_name":"Stephen D. Brown","orcid":"https://orcid.org/0009-0009-8329-1504"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Stephen Brown","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Department of Electrical and Computer Engineering, 10 King\u00bfs College Road, Ontario, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021489497"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":1.8467,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85614208,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"23","issue":null,"first_page":"294","last_page":"301"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8542804718017578},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.842961311340332},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8082552552223206},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6042969822883606},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4954308271408081},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.4784422218799591},{"id":"https://openalex.org/keywords/replication","display_name":"Replication (statistics)","score":0.4638497829437256},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4310503900051117},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42211610078811646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4012349843978882},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33127903938293457},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21444907784461975},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1943875551223755},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1453496217727661},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09411746263504028},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.07996296882629395}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8542804718017578},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.842961311340332},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8082552552223206},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6042969822883606},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4954308271408081},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.4784422218799591},{"id":"https://openalex.org/C12590798","wikidata":"https://www.wikidata.org/wiki/Q3933199","display_name":"Replication (statistics)","level":2,"score":0.4638497829437256},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4310503900051117},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42211610078811646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4012349843978882},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33127903938293457},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21444907784461975},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1943875551223755},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1453496217727661},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09411746263504028},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.07996296882629395},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2009.5272286","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272286","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1543657314","https://openalex.org/W1557355787","https://openalex.org/W1580684925","https://openalex.org/W2005082107","https://openalex.org/W2032309817","https://openalex.org/W2080285119","https://openalex.org/W2113843141","https://openalex.org/W2144907677","https://openalex.org/W2151406013","https://openalex.org/W2165100134","https://openalex.org/W2169725869","https://openalex.org/W2170675383","https://openalex.org/W2295333953","https://openalex.org/W3144114163"],"related_works":["https://openalex.org/W2371266106","https://openalex.org/W2117382851","https://openalex.org/W3006505070","https://openalex.org/W2382449560","https://openalex.org/W2767298477","https://openalex.org/W2110432562","https://openalex.org/W2117864619","https://openalex.org/W2025344","https://openalex.org/W2090337950","https://openalex.org/W2104121286"],"abstract_inverted_index":{"Capacity":[0],"of":[1,10,92,126,153,160,168,171],"FPGAs":[2,59,86],"has":[3],"grown":[4],"significantly,":[5],"leading":[6],"to":[7,35,109,119],"increased":[8,131,180],"complexity":[9],"designs":[11,79],"targeting":[12],"these":[13],"chips.":[14],"Traditional":[15],"FPGA":[16,73,140,145],"design":[17,111],"methodology":[18],"using":[19],"HDLs":[20],"is":[21,34],"no":[22],"longer":[23],"sufficient":[24],"and":[25,84,147,163,166],"new":[26],"methodologies":[27],"are":[28,46,54],"being":[29],"sought.":[30],"An":[31],"attractive":[32],"possibility":[33],"use":[36],"streaming":[37,82,104,127],"languages.":[38],"Streaming":[39],"languages":[40],"group":[41],"data":[42],"into":[43],"streams,":[44],"which":[45,64],"processed":[47],"by":[48,68,149],"computational":[49],"nodes":[50],"called":[51],"kernels.":[52],"They":[53],"suitable":[55],"for":[56,112,182],"implementation":[57],"in":[58,72,80],"because":[60],"they":[61],"expose":[62],"parallelism,":[63],"can":[65,76,106,129,142],"be":[66,107,130],"exploited":[67],"implementing":[69],"the":[70,102,139,151,158],"application":[71],"logic.":[74],"Designers":[75],"express":[77],"their":[78],"a":[81,89,169],"language":[83,105],"target":[85],"without":[87],"needing":[88],"detailed":[90],"understanding":[91],"digital":[93],"logic":[94],"design.":[95],"In":[96],"this":[97],"paper":[98],"we":[99],"show":[100,123],"how":[101],"Brook":[103],"used":[108],"simplify":[110],"FPGAs,":[113],"while":[114],"providing":[115],"reasonable":[116],"performance":[117,148,165],"compared":[118],"other":[120],"methodologies.":[121],"We":[122,156,173],"that":[124,175],"throughput":[125,176],"applications":[128],"through":[132],"automatic":[133],"kernel":[134,154],"replication.":[135,155],"Using":[136],"our":[137,161],"compiler,":[138],"designer":[141],"trade":[143],"off":[144],"area":[146,167],"changing":[150],"amount":[152],"describe":[157],"details":[159],"compiler":[162],"present":[164],"set":[170],"benchmarks.":[172],"found":[174],"scales":[177],"well":[178],"with":[179],"replication":[181],"most":[183],"applications.":[184]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}