{"id":"https://openalex.org/W2018513292","doi":"https://doi.org/10.1109/fpl.2009.5272279","title":"Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol","display_name":"Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2018513292","doi":"https://doi.org/10.1109/fpl.2009.5272279","mag":"2018513292"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2009.5272279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060626530","display_name":"Diana G\u00f6hringer","orcid":"https://orcid.org/0000-0003-2571-8441"},"institutions":[{"id":"https://openalex.org/I2801697266","display_name":"FOM University of Applied Sciences for Economics and Management","ror":"https://ror.org/05m3vpd98","country_code":"DE","type":"education","lineage":["https://openalex.org/I2801697266"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Diana Gohringer","raw_affiliation_strings":["FGAN-FOM, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FGAN-FOM, Germany","institution_ids":["https://openalex.org/I2801697266"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011552194","display_name":"Bin Liu","orcid":"https://orcid.org/0000-0002-0363-0863"},"institutions":[{"id":"https://openalex.org/I2801697266","display_name":"FOM University of Applied Sciences for Economics and Management","ror":"https://ror.org/05m3vpd98","country_code":"DE","type":"education","lineage":["https://openalex.org/I2801697266"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bin Liu","raw_affiliation_strings":["FGAN-FOM, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FGAN-FOM, Germany","institution_ids":["https://openalex.org/I2801697266"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108437484","display_name":"Michael H\u00fcbner","orcid":"https://orcid.org/0000-0002-1790-3869"},"institutions":[{"id":"https://openalex.org/I102335020","display_name":"Karlsruhe Institute of Technology","ror":"https://ror.org/04t3en479","country_code":"DE","type":"education","lineage":["https://openalex.org/I102335020","https://openalex.org/I1305996414"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Hubner","raw_affiliation_strings":["ITIV, Universit\u00e4t Karlsruhe, Germany","[ITIV-Universit\u00e4t Karlsruhe (TH), Germany]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITIV, Universit\u00e4t Karlsruhe, Germany","institution_ids":[]},{"raw_affiliation_string":"[ITIV-Universit\u00e4t Karlsruhe (TH), Germany]","institution_ids":["https://openalex.org/I102335020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024739574","display_name":"J\u00fcrgen Becker","orcid":"https://orcid.org/0000-0002-5082-5487"},"institutions":[{"id":"https://openalex.org/I102335020","display_name":"Karlsruhe Institute of Technology","ror":"https://ror.org/04t3en479","country_code":"DE","type":"education","lineage":["https://openalex.org/I102335020","https://openalex.org/I1305996414"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Becker","raw_affiliation_strings":["ITIV, Universit\u00e4t Karlsruhe, Germany","[ITIV-Universit\u00e4t Karlsruhe (TH), Germany]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITIV, Universit\u00e4t Karlsruhe, Germany","institution_ids":[]},{"raw_affiliation_string":"[ITIV-Universit\u00e4t Karlsruhe (TH), Germany]","institution_ids":["https://openalex.org/I102335020"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"320","last_page":"325"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9861000180244446,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.975600004196167,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7754883766174316},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6120057702064514},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6068853139877319},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5939434766769409},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5744372010231018},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.548848032951355},{"id":"https://openalex.org/keywords/circuit-switching","display_name":"Circuit switching","score":0.520904004573822},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5019097328186035},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4870198369026184},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4758836328983307},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.4592447578907013},{"id":"https://openalex.org/keywords/communications-protocol","display_name":"Communications protocol","score":0.45124077796936035},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43423518538475037},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4110499322414398},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3683391213417053},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2601751685142517},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.22486111521720886}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7754883766174316},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6120057702064514},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6068853139877319},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5939434766769409},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5744372010231018},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.548848032951355},{"id":"https://openalex.org/C74294265","wikidata":"https://www.wikidata.org/wiki/Q506273","display_name":"Circuit switching","level":2,"score":0.520904004573822},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5019097328186035},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4870198369026184},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4758836328983307},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.4592447578907013},{"id":"https://openalex.org/C12269588","wikidata":"https://www.wikidata.org/wiki/Q132364","display_name":"Communications protocol","level":2,"score":0.45124077796936035},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43423518538475037},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4110499322414398},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3683391213417053},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2601751685142517},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.22486111521720886},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpl.2009.5272279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2009.5272279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:fraunhofer.de:N-125652","is_oa":false,"landing_page_url":"http://publica.fraunhofer.de/documents/N-125652.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400801","display_name":"Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Fraunhofer IITB","raw_type":"Conference Paper"},{"id":"pmh:oai:publica.fraunhofer.de:publica/364274","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/364274","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1548168045","https://openalex.org/W1984520032","https://openalex.org/W2008019170","https://openalex.org/W2021864915","https://openalex.org/W2035541071","https://openalex.org/W2098241733","https://openalex.org/W2111263794","https://openalex.org/W2118542578","https://openalex.org/W2151233254","https://openalex.org/W2154323564","https://openalex.org/W2540500304","https://openalex.org/W4253638730","https://openalex.org/W6676549523"],"related_works":["https://openalex.org/W4238242975","https://openalex.org/W2012652058","https://openalex.org/W2135981148","https://openalex.org/W2124316266","https://openalex.org/W2388672758","https://openalex.org/W2065289416","https://openalex.org/W2144357574","https://openalex.org/W2754086592","https://openalex.org/W2030153835","https://openalex.org/W4230458348"],"abstract_inverted_index":{"Multiprocessor":[0],"System-on-Chip":[1],"is":[2],"a":[3,104,108,117],"promising":[4],"realization":[5],"alternative":[6],"for":[7,107],"the":[8,15,55,69,73,90,130],"next":[9],"generation":[10],"of":[11,58,72,92],"computing":[12,23],"architectures":[13],"providing":[14],"required":[16],"data":[17,74,140],"processing":[18,36,128],"performance":[19,22,139],"in":[20,44],"high":[21],"applications.":[24],"Numerous":[25],"scientists":[26],"from":[27,89,126],"industry":[28],"and":[29,33,38,120,141],"academic":[30],"institutions":[31],"investigate":[32],"develop":[34],"novel":[35,105],"elements":[37,62],"accelerators":[39],"as":[40,114,116],"can":[41],"be":[42,65,76],"seen":[43],"real":[45],"devices":[46],"like":[47,138],"IBM's":[48],"Cell":[49],"or":[50,81],"nVIDIA's":[51],"Tesla":[52],"GPU.":[53],"Nevertheless,":[54],"on-chip":[56],"communication":[57,84,113],"these":[59],"multiple":[60],"processor":[61],"has":[63],"to":[64,68,75,96],"optimized":[66],"tailored":[67],"actual":[70],"requirement":[71],"processed.":[77],"Network-on-Chip":[78],"(NoC),":[79],"Bus-based":[80],"even":[82],"heterogeneous":[83,121],"on":[85,133],"chip":[86],"often":[87],"suffer":[88],"fact":[91],"being":[93],"inflexible":[94],"due":[95],"their":[97],"fixed":[98],"physical":[99],"realization.":[100],"This":[101],"paper":[102],"presents":[103],"approach":[106],"NoC,":[109],"exploiting":[110,129],"circuit-and":[111],"packed-switched":[112],"well":[115],"run-time":[118],"adaptive":[119],"topology.":[122],"An":[123],"application":[124],"scenario":[125],"image":[127],"implemented":[131],"NoC":[132],"an":[134],"FPGA":[135],"delivers":[136],"results":[137],"hardware":[142],"costs.":[143]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}