{"id":"https://openalex.org/W2148320667","doi":"https://doi.org/10.1109/fpl.2008.4630046","title":"Combating process variation on FPGAS with a precise at-speed delay measurement method","display_name":"Combating process variation on FPGAS with a precise at-speed delay measurement method","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2148320667","doi":"https://doi.org/10.1109/fpl.2008.4630046","mag":"2148320667"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4630046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051758515"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.3466,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70800873,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"703","last_page":"704"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8709322214126587},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.845795750617981},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.7604354619979858},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6837082505226135},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6588814854621887},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.634708046913147},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.6240830421447754},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4495465159416199},{"id":"https://openalex.org/keywords/measure","display_name":"Measure (data warehouse)","score":0.4494393765926361},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.44629037380218506},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44378310441970825},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40117451548576355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3743816316127777},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3647070825099945},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3213655948638916},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17442303895950317},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11884137988090515}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8709322214126587},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.845795750617981},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.7604354619979858},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6837082505226135},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6588814854621887},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.634708046913147},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.6240830421447754},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4495465159416199},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.4494393765926361},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.44629037380218506},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44378310441970825},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40117451548576355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3743816316127777},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3647070825099945},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3213655948638916},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17442303895950317},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11884137988090515},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4630046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2016712281","https://openalex.org/W2096227207","https://openalex.org/W2141682861"],"related_works":["https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W1973774436","https://openalex.org/W3151506308","https://openalex.org/W2110367374","https://openalex.org/W2160859600","https://openalex.org/W3092420867","https://openalex.org/W2042032654","https://openalex.org/W2115729972","https://openalex.org/W2158291854"],"abstract_inverted_index":{"The":[0,53,74],"goal":[1],"of":[2,15,37,41,58,96,107],"this":[3,84],"PhD":[4],"project":[5],"is":[6,35,70,76],"to":[7,11,64,77,90,100],"devise":[8],"a":[9,30],"way":[10],"combat":[12],"the":[13,39,56,88,92,104],"effect":[14],"process":[16,108],"variation":[17],"on":[18,43,83],"propagation":[19],"delays":[20,40],"in":[21,98],"modern":[22],"FPGAs.":[23],"Through":[24],"our":[25],"research,":[26],"we":[27],"have":[28],"devised":[29],"novel":[31],"measurement":[32],"method":[33,54,85],"that":[34],"capable":[36],"measuring":[38],"components":[42,81],"FPGAs":[44,99],"with":[45],"picosecond":[46],"timing":[47],"resolution":[48],"and":[49,62,86,94],"fine":[50],"spatial":[51],"granularity.":[52],"avoids":[55],"use":[57,87],"external":[59],"test":[60,79],"equipment":[61],"able":[63],"measure":[65],"stochastic":[66],"delay":[67],"variability,":[68],"which":[69],"becoming":[71],"increasingly":[72],"significant.":[73],"aim":[75],"exhaustively":[78],"FPGA":[80],"based":[82],"results":[89],"optimise":[91],"placement":[93],"routing":[95],"circuits":[97],"maximise":[101],"performance":[102],"under":[103],"negative":[105],"influence":[106],"variation.":[109]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
