{"id":"https://openalex.org/W2122767199","doi":"https://doi.org/10.1109/fpl.2008.4630023","title":"A hardware compilation flow for instance-specific VLIW cores","display_name":"A hardware compilation flow for instance-specific VLIW cores","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2122767199","doi":"https://doi.org/10.1109/fpl.2008.4630023","mag":"2122767199"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4630023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041162707","display_name":"Markus Koester","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119109","display_name":"Indiana University Bloomington","ror":"https://ror.org/02k40bc56","country_code":"US","type":"education","lineage":["https://openalex.org/I4210119109","https://openalex.org/I592451"]},{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"Markus Koester","raw_affiliation_strings":["Department of Computer Science, Indiana University, Bloomington, IN, USA","Dept of Comput., Imperial Coll. London, London"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Indiana University, Bloomington, IN, USA","institution_ids":["https://openalex.org/I4210119109"]},{"raw_affiliation_string":"Dept of Comput., Imperial Coll. London, London","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043749887","display_name":"Wayne Luk","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Department of Computing, Imperial College London, UK","Dept of Comput., Imperial Coll. London, London"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept of Comput., Imperial Coll. London, London","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103464606","display_name":"Geoffrey Brown","orcid":"https://orcid.org/0009-0004-6180-7673"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]},{"id":"https://openalex.org/I4210119109","display_name":"Indiana University Bloomington","ror":"https://ror.org/02k40bc56","country_code":"US","type":"education","lineage":["https://openalex.org/I4210119109","https://openalex.org/I592451"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Geoffrey Brown","raw_affiliation_strings":["Department of Computing, Imperial College London, UK","Dept. of Computer Science, Indiana University, Bloomington, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Computer Science, Indiana University, Bloomington, USA","institution_ids":["https://openalex.org/I4210119109"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5041162707"],"corresponding_institution_ids":["https://openalex.org/I4210119109","https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.7729,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.91181053,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"5","issue":null,"first_page":"619","last_page":"622"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8668715357780457},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8493396043777466},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7543976306915283},{"id":"https://openalex.org/keywords/ansi-c","display_name":"ANSI C","score":0.515942394733429},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.44426125288009644},{"id":"https://openalex.org/keywords/high-level-programming-language","display_name":"High-level programming language","score":0.4414178729057312},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.43721282482147217},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.426637202501297},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4221717119216919},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38389503955841064},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37032437324523926},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3368617296218872},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.31573373079299927},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08215728402137756}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8668715357780457},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8493396043777466},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7543976306915283},{"id":"https://openalex.org/C158100120","wikidata":"https://www.wikidata.org/wiki/Q1931402","display_name":"ANSI C","level":3,"score":0.515942394733429},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.44426125288009644},{"id":"https://openalex.org/C19024347","wikidata":"https://www.wikidata.org/wiki/Q211496","display_name":"High-level programming language","level":3,"score":0.4414178729057312},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.43721282482147217},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.426637202501297},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4221717119216919},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38389503955841064},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37032437324523926},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3368617296218872},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.31573373079299927},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08215728402137756}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4630023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.47999998927116394,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1506585561","https://openalex.org/W1558558660","https://openalex.org/W2013286553","https://openalex.org/W2158583421","https://openalex.org/W3147835733","https://openalex.org/W6793159789"],"related_works":["https://openalex.org/W2790678706","https://openalex.org/W4281926497","https://openalex.org/W3022794856","https://openalex.org/W2026383319","https://openalex.org/W2126613634","https://openalex.org/W2775810811","https://openalex.org/W3142225536","https://openalex.org/W2427933582","https://openalex.org/W2182764230","https://openalex.org/W2954318817"],"abstract_inverted_index":{"Hardware":[0],"compilers":[1],"for":[2,61],"high-level":[3,41,95],"programming":[4,42],"languages":[5],"are":[6,135],"important":[7],"tools":[8],"to":[9,30,58,137],"reduce":[10],"the":[11,51,69,100,103,112,116,119,124],"design":[12,104],"productivity":[13],"gap":[14],"in":[15,39],"hardware":[16,22,33,63,83],"development.":[17],"In":[18],"this":[19],"paper":[20],"a":[21,32,37,40,62,65,106],"compilation":[23],"approach":[24],"is":[25,28,54,74,85,91,108],"described,":[26],"which":[27,90,110],"able":[29],"generate":[31],"description":[34],"based":[35],"on":[36],"specification":[38,53],"language":[43],"such":[44],"as":[45,115,123],"ANSI":[46],"C.":[47],"No":[48],"modification":[49],"of":[50,102,131],"program":[52,96],"required,":[55],"allowing":[56],"it":[57],"be":[59],"suitable":[60],"and":[64,118],"software":[66,139],"implementation":[67,84],"at":[68],"same":[70],"time.":[71],"The":[72,81,126],"parallelism":[73],"extracted":[75],"by":[76,93],"using":[77],"VLIW":[78,88,129],"optimization":[79],"techniques.":[80],"generated":[82],"an":[86],"instance-specific":[87,128],"core,":[89],"defined":[92],"its":[94],"specification.":[97],"To":[98],"demonstrate":[99],"principle":[101],"flow,":[105],"prototype":[107],"presented":[109],"uses":[111],"VEX":[113],"compiler":[114],"front-end":[117],"Handel-C":[120],"tool":[121],"chain":[122],"back-end.":[125],"resulting":[127],"cores":[130],"several":[132],"test":[133],"functions":[134],"compared":[136],"equivalent":[138],"implementations.":[140]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}