{"id":"https://openalex.org/W2089203444","doi":"https://doi.org/10.1109/fpl.2008.4629990","title":"A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck","display_name":"A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2089203444","doi":"https://doi.org/10.1109/fpl.2008.4629990","mag":"2089203444"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4629990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5106183100","display_name":"Claudio Brunelli","orcid":null},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Claudio Brunelli","raw_affiliation_strings":["Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere","institution_ids":["https://openalex.org/I150589677"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056978552","display_name":"Fabio Garzia","orcid":"https://orcid.org/0000-0003-2597-4429"},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Fabio Garzia","raw_affiliation_strings":["Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere","institution_ids":["https://openalex.org/I150589677"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015654935","display_name":"Carmelo Giliberto","orcid":null},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Carmelo Giliberto","raw_affiliation_strings":["Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere","institution_ids":["https://openalex.org/I150589677"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I150589677","display_name":"Tampere University of Applied Sciences","ror":"https://ror.org/00bwtjf83","country_code":"FI","type":"education","lineage":["https://openalex.org/I150589677"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]},{"raw_affiliation_string":"Dept. of Inf. Technol., Tampere Univ. of Technol., Tampere","institution_ids":["https://openalex.org/I150589677"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7266,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.86031578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"487","last_page":"490"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8122843503952026},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6289626359939575},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5472558736801147},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.5432807207107544},{"id":"https://openalex.org/keywords/direct-memory-access","display_name":"Direct memory access","score":0.5386185050010681},{"id":"https://openalex.org/keywords/local-bus","display_name":"Local bus","score":0.5148965120315552},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5092211961746216},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.48435863852500916},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.47473081946372986},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.45494768023490906},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4361618161201477},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.43547549843788147},{"id":"https://openalex.org/keywords/address-bus","display_name":"Address bus","score":0.42175182700157166},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.41872546076774597},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4034266173839569},{"id":"https://openalex.org/keywords/control-bus","display_name":"Control bus","score":0.375969797372818},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33872130513191223},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.28721731901168823},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28231945633888245},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.27748292684555054},{"id":"https://openalex.org/keywords/transfer","display_name":"Transfer (computing)","score":0.2322838008403778}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8122843503952026},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6289626359939575},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5472558736801147},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.5432807207107544},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.5386185050010681},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.5148965120315552},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5092211961746216},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.48435863852500916},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.47473081946372986},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.45494768023490906},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4361618161201477},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.43547549843788147},{"id":"https://openalex.org/C54714250","wikidata":"https://www.wikidata.org/wiki/Q178048","display_name":"Address bus","level":3,"score":0.42175182700157166},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.41872546076774597},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4034266173839569},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.375969797372818},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33872130513191223},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.28721731901168823},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28231945633888245},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.27748292684555054},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.2322838008403778},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4629990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.46000000834465027,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1498091004","https://openalex.org/W2542473914"],"related_works":["https://openalex.org/W2491097902","https://openalex.org/W4243333834","https://openalex.org/W2057195881","https://openalex.org/W2552325249","https://openalex.org/W1554378476","https://openalex.org/W2386568907","https://openalex.org/W4393076761","https://openalex.org/W2361382102","https://openalex.org/W2041174925","https://openalex.org/W2014336100"],"abstract_inverted_index":{"A":[0],"very":[1],"common":[2,21,35],"problem":[3],"which":[4,23,109],"affects":[5],"the":[6,14,17,42,49,54,57,60,67,83,95,130,135,147,183],"performance":[7],"of":[8,31,44,48,59,101,185],"bus-based":[9],"computing":[10],"systems":[11],"arises":[12],"from":[13,82,134],"fact":[15],"that":[16,169],"bus":[18,50,61,68,73],"is":[19,62,141,175],"a":[20,29,79,87,91,119,150,172,179,186],"resource":[22,36],"needs":[24],"to":[25,39,70,77,86,90,105,112,123,128,143,153,160,177],"be":[26],"shared":[27],"between":[28],"number":[30],"master":[32,69],"devices.":[33],"The":[34,99,138],"contention":[37],"forces":[38],"stall":[40],"temporarily":[41],"execution":[43,184],"one":[45],"or":[46],"more":[47],"masters,":[51],"slowing":[52],"down":[53],"execution.":[55],"Moreover,":[56],"width":[58],"usually":[63],"relatively":[64],"small,":[65],"forcing":[66],"perform":[71],"several":[72],"cycles":[74],"in":[75,149,158,163,182],"order":[76,159],"transfer":[78],"data":[80,145],"block":[81],"main":[84,136],"memory":[85,132,148,156],"peripheral":[88],"(or":[89],"processing":[92],"element),":[93],"and":[94,107],"other":[96],"way":[97],"around.":[98],"combination":[100],"these":[102],"factors":[103],"leads":[104],"problems":[106],"inefficiencies":[108],"designers":[110],"need":[111],"solve.":[113],"In":[114],"this":[115],"paper":[116],"we":[117],"present":[118],"dedicated":[120],"hardware":[121],"used":[122],"allow":[124],"an":[125,164],"external":[126],"accelerator":[127],"access":[129,161],"system":[131],"independently":[133],"microprocessor.":[137],"proposed":[139],"device":[140],"able":[142],"exchange":[144],"with":[146],"DMA-like":[151],"fashion,":[152],"generate":[154],"properly":[155],"addresses":[157],"it":[162,174],"efficient":[165],"way.":[166],"Results":[167],"show":[168],"using":[170],"such":[171],"solution":[173],"possible":[176],"reach":[178],"considerable":[180],"speed-up":[181],"given":[187],"algorithm.":[188]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
