{"id":"https://openalex.org/W2114452736","doi":"https://doi.org/10.1109/fpl.2008.4629975","title":"The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays","display_name":"The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2114452736","doi":"https://doi.org/10.1109/fpl.2008.4629975","mag":"2114452736"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4629975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021641125","display_name":"Ping Chen","orcid":"https://orcid.org/0000-0003-0684-9665"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ping Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ryerson University, Toronto, ONT, Canada","Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ryerson University, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068830776","display_name":"Andy Ye","orcid":"https://orcid.org/0000-0002-2959-5736"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andy Ye","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ryerson University, Toronto, ONT, Canada","Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ryerson University, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5021641125"],"corresponding_institution_ids":["https://openalex.org/I530967"],"apc_list":null,"apc_paid":null,"fwci":0.339,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65673959,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"12","issue":null,"first_page":"427","last_page":"430"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7702884674072266},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7320560216903687},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6924445629119873},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5622326135635376},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.47795534133911133},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.46148911118507385},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42911022901535034},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4173280894756317},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4039291441440582},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32819753885269165}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7702884674072266},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7320560216903687},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6924445629119873},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5622326135635376},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.47795534133911133},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.46148911118507385},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42911022901535034},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4173280894756317},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4039291441440582},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32819753885269165},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2008.4629975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.567.5462","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.567.5462","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.ryerson.ca/~aye/Phoebe_fpl2008.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1481821439","https://openalex.org/W1523051745","https://openalex.org/W1887556625","https://openalex.org/W1998449406","https://openalex.org/W2090068045","https://openalex.org/W2104449965","https://openalex.org/W2113645429","https://openalex.org/W2119061775","https://openalex.org/W2126255765","https://openalex.org/W2130227050","https://openalex.org/W2140956115","https://openalex.org/W2140998818","https://openalex.org/W2165099691","https://openalex.org/W2168225933","https://openalex.org/W6639711652","https://openalex.org/W6662167024"],"related_works":["https://openalex.org/W3146360095","https://openalex.org/W2295734895","https://openalex.org/W2014521732","https://openalex.org/W3012528295","https://openalex.org/W2024574431","https://openalex.org/W2387100797","https://openalex.org/W2184011203","https://openalex.org/W2787072969","https://openalex.org/W1522517392","https://openalex.org/W1554938446"],"abstract_inverted_index":{"The":[0,165],"increased":[1],"use":[2,75],"of":[3,34,42,64,76,97,106,147,172,193],"multi-bit":[4,13,35,55,83,148],"processing":[5],"elements":[6,84],"such":[7],"as":[8],"digital":[9],"signal":[10],"processors,":[11],"multipliers,":[12],"addressable":[14],"memory":[15,47,67,126,137,155],"cells,":[16],"and":[17,177],"CPU":[18],"cores":[19],"has":[20,49],"presented":[21],"new":[22],"opportunities":[23],"for":[24,57,81],"Field-Programmable":[25],"Gate":[26],"Array":[27],"(FPGA)":[28],"architects":[29],"to":[30,37,53,73,85,119,158,188],"utilize":[31],"the":[32,39,62,74,95,103,112,120,144,190],"regularity":[33,56],"signals":[36],"increase":[38,189],"area":[40,104,121,146,163,191],"efficiency":[41,105,192],"FPGAs.":[43,107,128],"In":[44,89,129],"particular,":[45,130],"configuration":[46,66,125,136,154],"sharing":[48,68,127,156],"been":[50],"traditionally":[51],"used":[52,187],"exploit":[54],"area.":[58],"We":[59],"observe":[60],"that":[61,111,179],"process":[63],"creating":[65],"routing":[69,87,149,195],"resources":[70,150],"often":[71],"leads":[72],"much":[77],"sparser":[78],"switch":[79,100,114,140,181],"patterns":[80,101,115,141],"connecting":[82],"their":[86],"tracks.":[88],"this":[90],"work,":[91],"we":[92],"empirically":[93],"evaluate":[94],"effect":[96],"these":[98],"sparse":[99,113,139],"on":[102],"It":[108],"is":[109],"shown":[110],"alone":[116],"contribute":[117],"significantly":[118],"reduction":[122],"observed":[123],"in":[124,162],"our":[131],"experiments":[132],"show":[133],"that,":[134],"without":[135],"sharing,":[138],"can":[142,184],"reduce":[143],"implementation":[145],"by":[151],"10.4%":[152],"while":[153],"contributes":[157],"an":[159],"additional":[160],"1.2%":[161],"savings.":[164],"observation":[166],"holds":[167],"over":[168],"a":[169],"wide":[170],"range":[171],"connection":[173],"block":[174],"flexibility":[175],"values":[176],"demonstrates":[178],"efficient":[180],"pattern":[182],"designs":[183],"be":[185],"effectively":[186],"FPGA":[194],"resources.":[196]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
