{"id":"https://openalex.org/W2106942255","doi":"https://doi.org/10.1109/fpl.2008.4629963","title":"Floating point datapath synthesis for FPGAs","display_name":"Floating point datapath synthesis for FPGAs","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2106942255","doi":"https://doi.org/10.1109/fpl.2008.4629963","mag":"2106942255"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4629963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629963","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082265695","display_name":"Martin Langhammer","orcid":"https://orcid.org/0000-0001-8206-2077"},"institutions":[{"id":"https://openalex.org/I4210094575","display_name":"Altera (United Kingdom)","ror":"https://ror.org/00m96gg93","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210094575"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Martin Langhammer","raw_affiliation_strings":["Altera UK Limited, High Wycombe, Buckinghamshire, UK","Altera UK Ltd., High Wycombe"],"affiliations":[{"raw_affiliation_string":"Altera UK Limited, High Wycombe, Buckinghamshire, UK","institution_ids":["https://openalex.org/I4210094575"]},{"raw_affiliation_string":"Altera UK Ltd., High Wycombe","institution_ids":["https://openalex.org/I4210094575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5082265695"],"corresponding_institution_ids":["https://openalex.org/I4210094575"],"apc_list":null,"apc_paid":null,"fwci":8.4607,"has_fulltext":false,"cited_by_count":53,"citation_normalized_percentile":{"value":0.9788865,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"355","last_page":"360"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9925228357315063},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.8077032566070557},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7735466361045837},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7583495378494263},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7344788312911987},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.6859732866287231},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5991445779800415},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5426713228225708},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.5405210256576538},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4551527202129364},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.43792539834976196},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4339079260826111},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.4117889404296875},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37499475479125977},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33908581733703613},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.25949621200561523},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1527176797389984}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9925228357315063},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.8077032566070557},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7735466361045837},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7583495378494263},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7344788312911987},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.6859732866287231},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5991445779800415},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5426713228225708},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.5405210256576538},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4551527202129364},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.43792539834976196},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4339079260826111},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.4117889404296875},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37499475479125977},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33908581733703613},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25949621200561523},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1527176797389984},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4629963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629963","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1991973578","https://openalex.org/W2105158708","https://openalex.org/W2111345110"],"related_works":["https://openalex.org/W3116924726","https://openalex.org/W3150370983","https://openalex.org/W2106942255","https://openalex.org/W1861262881","https://openalex.org/W3177218348","https://openalex.org/W2065321717","https://openalex.org/W2156524298","https://openalex.org/W17610788","https://openalex.org/W2752065998","https://openalex.org/W2013660188"],"abstract_inverted_index":{"Floating":[0],"point":[1,18,48],"arithmetic":[2],"is":[3,31,59],"used":[4],"extensively":[5],"in":[6,69],"many":[7],"applications":[8],"across":[9],"multiple":[10,29],"market":[11],"segments.":[12],"While":[13],"high":[14,63],"performance":[15,64],"IEEE754":[16],"floating":[17,47],"cores":[19,30],"are":[20],"available":[21],"for":[22,51],"FPGAs,":[23,52],"a":[24,43,60],"large":[25],"datapath":[26,49,55],"consisting":[27],"of":[28],"resource":[32],"intensive,":[33],"with":[34],"often":[35],"poor":[36],"system":[37],"performance.":[38],"This":[39],"paper":[40],"will":[41],"introduce":[42],"new":[44],"approach":[45],"to":[46],"design":[50],"using":[53],"fused":[54],"synthesis.":[56],"The":[57],"result":[58],"more":[61],"balanced,":[62],"implementation,":[65],"typically":[66],"saving":[67],"50%":[68],"both":[70],"logic":[71],"resources":[72],"and":[73,84],"latency.":[74],"Using":[75],"Stratix":[76],"reg":[77],"3SE260":[78],"devices,":[79],"50":[80],"GFLOPs":[81,86],"double":[82],"precision":[83,88],"125":[85],"single":[87],"can":[89],"be":[90],"realized.":[91]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}