{"id":"https://openalex.org/W2151872233","doi":"https://doi.org/10.1109/fpl.2008.4629935","title":"An analytical model describing the relationships between logic architecture and FPGA density","display_name":"An analytical model describing the relationships between logic architecture and FPGA density","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2151872233","doi":"https://doi.org/10.1109/fpl.2008.4629935","mag":"2151872233"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4629935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111918578","display_name":"Andrew Lam","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andrew Lam","raw_affiliation_strings":["Elec. and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Elec. and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Steven J.E. Wilton","raw_affiliation_strings":["Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107994859","display_name":"Philip H. W. Leong","orcid":"https://orcid.org/0000-0002-3923-3499"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Philip Leong","raw_affiliation_strings":["Elec. and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Elec. and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Department of Computing, Imperial College London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.642,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.97836929,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"221","last_page":"226"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9081632494926453},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8498650789260864},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6979429721832275},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.690590500831604},{"id":"https://openalex.org/keywords/cluster","display_name":"Cluster (spacecraft)","score":0.5839298963546753},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5545298457145691},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5412982702255249},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5045896768569946},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4984149932861328},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4916430115699768},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45023828744888306},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43335655331611633},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4249861240386963},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3738861083984375},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3564569354057312},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3387315571308136},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.22334593534469604},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20932963490486145},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15406736731529236}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9081632494926453},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8498650789260864},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6979429721832275},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.690590500831604},{"id":"https://openalex.org/C164866538","wikidata":"https://www.wikidata.org/wiki/Q367351","display_name":"Cluster (spacecraft)","level":2,"score":0.5839298963546753},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5545298457145691},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5412982702255249},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5045896768569946},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4984149932861328},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4916430115699768},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45023828744888306},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43335655331611633},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4249861240386963},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3738861083984375},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3564569354057312},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3387315571308136},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.22334593534469604},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20932963490486145},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15406736731529236},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpl.2008.4629935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.140.9457","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.9457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/analy_fpl08.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.224.8779","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.224.8779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/%7Estevew/papers/pdf/fpl08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1590243758","https://openalex.org/W1762720839","https://openalex.org/W1970296212","https://openalex.org/W1989477191","https://openalex.org/W1991530123","https://openalex.org/W2010988671","https://openalex.org/W2015540924","https://openalex.org/W2029541370","https://openalex.org/W2039288205","https://openalex.org/W2051503913","https://openalex.org/W2056836363","https://openalex.org/W2110265185","https://openalex.org/W2113645429","https://openalex.org/W2143067779","https://openalex.org/W4241806018","https://openalex.org/W6638025642"],"related_works":["https://openalex.org/W2135636985","https://openalex.org/W2003435315","https://openalex.org/W4379115868","https://openalex.org/W2149339590","https://openalex.org/W2139569078","https://openalex.org/W4231267350","https://openalex.org/W4252227487","https://openalex.org/W2170504327","https://openalex.org/W2063686821","https://openalex.org/W2526300902"],"abstract_inverted_index":{"This":[0,73],"paper":[1],"describes":[2],"an":[3,21],"analytical":[4],"model,":[5],"based":[6],"principally":[7],"on":[8],"Rentpsilas":[9],"Rule,":[10],"that":[11,46,68],"relates":[12,27],"logic":[13,45],"architectural":[14],"parameters":[15],"to":[16,41,64,91],"the":[17,25,28,31,35,42,56,77,81,96],"area":[18],"efficiency":[19],"of":[20,37,44,58,80,98],"FPGA.":[22],"In":[23],"particular,":[24],"model":[26],"lookup-table":[29,52],"size,":[30,33],"cluster":[32,40],"and":[34,53,55,94],"number":[36,57],"inputs":[38,60],"per":[39,61],"amount":[43],"can":[47],"be":[48],"packed":[49],"into":[50],"each":[51],"cluster,":[54],"used":[59],"cluster.":[62],"Comparison":[63],"experimental":[65],"results":[66],"show":[67],"our":[69],"models":[70],"are":[71],"accurate.":[72],"accuracy":[74],"combined":[75],"with":[76],"simple":[78],"form":[79],"equations":[82],"make":[83],"them":[84],"a":[85],"powerful":[86],"tool":[87],"for":[88],"FPGA":[89,100],"architects":[90],"better":[92],"understand":[93],"guide":[95],"development":[97],"future":[99],"architectures.":[101]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}